Patents by Inventor Koichiro Shindo

Koichiro Shindo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20240099013
    Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Applicant: Kioxia Corporation
    Inventors: Yoshiaki FUKUZUMI, Hideaki AOCHI, Mie MATSUO, Kenichiro YOSHII, Koichiro SHINDO, Kazushige KAWASAKI, Tomoya SANUKI
  • Semiconductor memory device including integrated control circuit and solid-state drive controller
    Patent number: 11871576
    Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: January 9, 2024
    Assignee: Kioxia Corporation
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi, Mie Matsuo, Kenichiro Yoshii, Koichiro Shindo, Kazushige Kawasaki, Tomoya Sanuki
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20210118898
    Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
    Type: Application
    Filed: December 7, 2020
    Publication date: April 22, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Yoshiaki FUKUZUMI, Hideaki AOCHI, Mie MATSUO, Kenichiro YOSHII, Koichiro SHINDO, Kazushige KAWASAKI, Tomoya SANUKI
  • Semiconductor memory device having a bonded circuit chip including a solid state drive controller connected to a control circuit
    Patent number: 10892269
    Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: January 12, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi, Mie Matsuo, Kenichiro Yoshii, Koichiro Shindo, Kazushige Kawasaki, Tomoya Sanuki
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20190273090
    Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
    Type: Application
    Filed: May 10, 2019
    Publication date: September 5, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Yoshiaki FUKUZUMI, Hideaki Aochi, Mie Matsuo, Kenichiro Yoshii, Koichiro Shindo, Kazushige Kawasaki, Tomoya Sanuki
  • SEMICONDUCTOR DEVICE AND DATA STORAGE APPARATUS
    Publication number: 20130114323
    Abstract: A semiconductor device according to an embodiment includes: a rectangular substrate having a first and a second principal surfaces ; a first semiconductor chip; one or more second semiconductor chips; and one or more third semiconductor chips. The substrate has first connection terminals connected to electrodes of the one or more second semiconductor chips, and third connection terminals electrically connected to the first connection terminals and connected to first electrodes of the first semiconductor chip, on a side of a first edge on the first principal surface. The substrate has second connection terminals connected to second electrodes of the one or more third semiconductor chips, and fourth connection terminals electrically connected to the second connection terminals and connected to electrodes of the first semiconductor chip, on a side of a second edge facing the first edge across the first semiconductor chip on the first principal surface.
    Type: Application
    Filed: August 30, 2012
    Publication date: May 9, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichiro Shindo, Masaji Iwamoto