Abstract: A semiconductor memory device includes a memory cell array that includes a plurality of memory cells, an SR timer that determines a cycle of self refresh of the memory cell, a refresh counter that generates an internal address signal of the memory cell which is a target of the self refresh, and a circuit that outputs a pulse active signal to continuously execute refresh operation in one cycle of the self refresh.

Abstract: A write circuit outputs a write con and to a memory cell in response to a data input signal. A decoder decodes an address input signal and outputs an address command to the memory cell. A counter outputs a signal to the decoder, the signal delaying decode timing in response to a control signal inputted at the time of a burn-in test. Therefore, the counter cancel a late write cycle by delaying an operation cycle of the decode timing against an operation cycle of a write command signal from the write circuit that is transmitted to the memory cell.

Abstract: In an input protection circuit for use in a semiconductor integrated circuit, a switch device 4, which becomes a conducting condition in response to an overvoltage applied between opposite ends thereof, is connected between a wiring conductor connecting an external input terminal 7 to an input node of an input first stage inverter 5 and an output node N3 of a logic gate 10 included within an internal circuit 3 provided in the semiconductor integrated circuit. When an overvoltage is applied to the external input terminal 7, the switch device 4 becomes the conducting condition so that the electric charge of the overvoltage applied to the external input terminal 7, is discharged through a MOS transistor QP6 or QN7 constituting the logic gate 10 within the internal circuit 3, to a power supply voltage line 1A or a ground potential line 2A which is laid within the internal circuit 3 for supplying a power supply voltage or a ground potential to the MOS transistor QP6 or QN7.