Patents by Inventor Koichiro Yuki
Koichiro Yuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240082559Abstract: A connector (50) includes a tubular member (52) and a base tube (58). A light-guiding tube (60) is drawn out from the base tube (58) toward the opposite side to the tubular member (52). An adapter (1) includes: a first connecting portion (10) that can be connected to and disconnected from a light source device (70); a second connecting portion (20) that can be connected to and disconnected from the connector (50); and a light-guiding member (30) that guides light emitted from the light source device (70) to a proximal end surface (61) of the tube (60).Type: ApplicationFiled: January 7, 2022Publication date: March 14, 2024Inventors: Takehiko YUKI, Masaya MUTSUKADO, Ken KANDA, Koichiro TOYOTA, Masahiro KINOSHITA, Osuke IWATA, Manabu MOCHIZUKI, Yasuo IMAMURA
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Patent number: 7465969Abstract: A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.Type: GrantFiled: June 12, 2006Date of Patent: December 16, 2008Assignee: Panasonic CorporationInventors: Teruhito Ohnishi, Koichiro Yuki, Tsuneichiro Sano, Tohru Saitoh, Ken Idota, Takahiro Kawashima, Shigeki Sawada
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Patent number: 7135721Abstract: The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 including an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.Type: GrantFiled: June 22, 2004Date of Patent: November 14, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kenji Toyoda, Koichiro Yuki, Takeshi Takagi, Teruhito Ohnishi, Minoru Kubo
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Publication number: 20060226446Abstract: A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.Type: ApplicationFiled: June 12, 2006Publication date: October 12, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Teruhito Ohnishi, Koichiro Yuki, Tsuneichiro Sano, Tohru Saitoh, Ken Idota, Takahiro Kawashima, Shigeki Sawada
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Patent number: 7091099Abstract: A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.Type: GrantFiled: March 24, 2004Date of Patent: August 15, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Teruhito Ohnishi, Koichiro Yuki, Tsuneichiro Sano, Tohru Saitoh, Ken Idota, Takahiro Kawashima, Shigeki Sawada
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Patent number: 7049198Abstract: An S1-yGey layer (where 0<y<1), an Si layer containing C, a gate insulating film and a gate electrode are formed in this order on a semiconductor substrate. An Si/SiGe heterojunction is formed between the Si and Si1-yGey layers. Since C is contained in the Si layer, movement, diffusion and segregation of Ge atoms in the S1-yGey layer can be suppressed. As a result, the Si/Si1-yGey interface can have its structural disorder eased and can be kept definite and planar. Thus, the mobility of carriers moving along the interface in the channel can be increased. That is to say, the thermal budget of the semiconductor device during annealing can be improved. Also, by grading the concentration profile of C, the diffusion of C into the gate insulating film can be suppressed and decline in reliability can be prevented.Type: GrantFiled: March 4, 2003Date of Patent: May 23, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koichiro Yuki, Tohru Saitoh, Minoru Kubo, Kiyoshi Ohnaka, Akira Asai, Koji Katayama
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Patent number: 6847062Abstract: In a semiconductor device functioning as a SiGeC-HBT, an emitter/base stacked portion 20 is formed on a Si epitaxially grown layer 2. The emitter/base stacked portion 20 includes: a SiGeC spacer layer 21; a SiGeC core base layer 22 containing boron at a high concentration, a SiGe cap layer 23; a Si cap layer 24, and an emitter layer 25 formed by introducing phosphorus into the Si cap layer 24 and the SiGe cap layer 23.Type: GrantFiled: April 15, 2003Date of Patent: January 25, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Teruhito Ohnishi, Koichiro Yuki, Shigeki Sawada, Keiichiro Shimizu, Koichi Hasegawa, Tohru Saitoh
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Patent number: 6847063Abstract: In a semiconductor device acting as an HBT, an emitter/base laminate portion is provided on a Si epitaxially grown layer in the SiGeC-HBT. The emitter/base laminate portion includes a SiGeC spacer layer, a SiGeC core base layer containing the boron, a Si cap layer, and an emitter layer formed by introducing phosphorous into the Si cap layer. The C content of the SiGeC spacer layer is equal to or lower than that of the SiGeC core base layer.Type: GrantFiled: April 15, 2003Date of Patent: January 25, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Teruhito Ohnishi, Koichiro Yuki, Shigeki Sawada, Keiichiro Shimizu, Koichi Hasegawa, Tohru Saitoh, Paul A. Clifton
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Publication number: 20040232441Abstract: The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 including an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.Type: ApplicationFiled: June 22, 2004Publication date: November 25, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kenji Toyoda, Koichiro Yuki, Takeshi Takagi, Teruhito Ohnishi, Minoru Kubo
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Patent number: 6821870Abstract: A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be narrower than the band gap of the conventional practical SiGe (the Ge content is about 10%), and good crystalline can be maintained after a heat treatment. As a result, a narrow band gap base with no practical inconvenience can be realized.Type: GrantFiled: August 21, 2002Date of Patent: November 23, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takeshi Takagi, Koichiro Yuki, Kenji Toyoda, Yoshihiko Kanzawa
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Publication number: 20040195655Abstract: A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.Type: ApplicationFiled: March 24, 2004Publication date: October 7, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Teruhito Ohnishi, Koichiro Yuki, Tsuneichiro Sano, Tohru Saitoh, Ken Idota, Takahiro Kawashima, Shigeki Sawada
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Patent number: 6759697Abstract: The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 including an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.Type: GrantFiled: June 16, 2003Date of Patent: July 6, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kenji Toyoda, Koichiro Yuki, Takeshi Takagi, Teruhito Ohnishi, Minoru Kubo
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Patent number: 6756278Abstract: A lateral heterojunction bipolar transistor comprises a first semiconductor layer in a mesa configuration disposed on an insulating layer, a second semiconductor layer formed by epitaxial growth on the side surfaces of the first semiconductor layer and having a band gap different from that of the first semiconductor layer, and a third semiconductor layer formed by epitaxial growth on the side surfaces of the second semiconductor layer and having a band gap different from that of the second semiconductor layer. The first semiconductor layer serves as a collector of a first conductivity type. At least a part of the second semiconductor layer serves as an internal base layer of a second conductivity type. At least a part of the third semiconductor layer serves as an emitter operating region of the first conductivity type. The diffusion of an impurity is suppressed in the internal base formed by epitaxial growth.Type: GrantFiled: October 11, 2002Date of Patent: June 29, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koichiro Yuki, Minoru Kubo
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Publication number: 20040065875Abstract: In a semiconductor device functioning as a SiGeC-HBT, an emitter/base stacked portion 20 is formed on a Si epitaxially grown layer 2. The emitter/base stacked portion 20 includes: a SiGeC spacer layer 21; a SiGeC core base layer 22 containing boron at a high concentration, a SiGe cap layer 23; a Si cap layer 24, and an emitter layer 25 formed by introducing phosphorus into the Si cap layer 24 and the SiGe cap layer 23.Type: ApplicationFiled: April 15, 2003Publication date: April 8, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Teruhito Ohnishi, Koichiro Yuki, Shigeki Sawada, Keiichiro Shimizu, Koichi Hasegawa, Tohru Saitoh
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Publication number: 20040065878Abstract: In a semiconductor device acting as an HBT, an emitter/base laminate portion is provided on a Si epitaxially grown layer in the SiGeC-HBT. The emitter/base laminate portion includes a SiGeC spacer layer, a SiGeC core base layer containing the boron, a Si cap layer, and an emitter layer formed by introducing phosphorous into the Si cap layer. The C content of the SiGeC spacer layer is equal to or lower than that of the SiGeC core base layer.Type: ApplicationFiled: April 15, 2003Publication date: April 8, 2004Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Teruhito Ohnishi, Koichiro Yuki, Shigeki Sawada, Keiichiro Shimizu, Koichi Hasegawa, Tohru Saitoh, Paul A. Clifton
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Patent number: 6713790Abstract: In the method for fabricating a semiconductor device of the present invention, a collector layer of a first conductivity type is formed in a region of a semiconductor substrate sandwiched by device isolation. A collector opening is formed through a first insulating layer deposited on the semiconductor substrate so that the range of the collector opening covers the collector layer and part of the device isolation. A semiconductor layer of a second conductivity type as an external base is formed on a portion of the semiconductor substrate located inside the collector opening, while junction leak prevention layers of the same conductivity type as the external base are formed in the semiconductor substrate. Thus, the active region is narrower than the collector opening reducing the transistor area, while minimizing junction leak.Type: GrantFiled: August 7, 2002Date of Patent: March 30, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akira Asai, Teruhito Oonishi, Takeshi Takagi, Tohru Saitoh, Yoshihiro Hara, Koichiro Yuki, Katsuya Nozawa, Yoshihiko Kanzawa, Koji Katayama, Yo Ichikawa
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Patent number: 6674150Abstract: A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be narrower than the band gap of the conventional practical SiGe (the Ge content is about 10%), and good crystalline can be maintained after a heat treatment. As a result, a narrow band gap base with no practical inconvenience can be realized.Type: GrantFiled: April 23, 2002Date of Patent: January 6, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takeshi Takagi, Koichiro Yuki, Kenji Toyoda, Yoshihiko Kanzawa
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Publication number: 20030213977Abstract: The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 including an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.Type: ApplicationFiled: June 16, 2003Publication date: November 20, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kenji Toyoda, Koichiro Yuki, Takeshi Takagi, Teruhito Ohnishi, Minoru Kubo
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Publication number: 20030162335Abstract: An S1-yGey layer (where 0<y<1), an Si layer containing C, a gate insulating film and a gate electrode are formed in this order on a semiconductor substrate. An Si/SiGe heterojunction is formed between the Si and Si1-yGey layers. Since C is contained in the Si layer, movement, diffusion and segregation of Ge atoms in the S1-yGey layer can be suppressed. As a result, the Si/Si1-yGey interface can have its structural disorder eased and can be kept definite and planar. Thus, the mobility of carriers moving along the interface in the channel can be increased. That is to say, the thermal budget of the semiconductor device during annealing can be improved. Also, by grading the concentration profile of C, the diffusion of C into the gate insulating film can be suppressed and decline in reliability can be prevented.Type: ApplicationFiled: March 4, 2003Publication date: August 28, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Koichiro Yuki, Tohru Saitoh, Minoru Kubo, Kiyoshi Ohnaka, Akira Asai, Koji Katayama
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Patent number: 6597016Abstract: An Si1−yGey layer (where 0<y<1), an Si layer containing C, a gate insulating film and a gate electrode are formed in this order on a semiconductor substrate. An Si/SiGe heterounction junction is formed between the Si and Si1−yGey layers. Since C is contained in the Si layer, movement, diffusion and segregation of Ge atoms in the Si1−yGey layer can be suppressed. As a result, the Si/Si1−yGey interface can have its structural disorder eased and can be kept definite and planar. Thus, the mobility of carriers moving along the interface in the channel can be increased. That is to say, the thermal budget of the semiconductor device during annealing can be improved. Also, by grading the concentration profile of C, the diffusion of C into the gate insulating film can be suppressed and decline in reliability can be prevented.Type: GrantFiled: January 13, 2000Date of Patent: July 22, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koichiro Yuki, Tohru Saitoh, Minoru Kubo, Kiyoshi Ohnaka, Akira Asai, Koji Katayama