Abstract: An imaging device includes a plurality of imaging elements, wherein each of the plurality of imaging elements includes: a plurality of pixels containing impurities of a first conductivity type; an element separation wall surrounding the plurality of pixels and provided so as to penetrate a semiconductor substrate; an on-chip lens provided above a light receiving surface of the semiconductor substrate so as to be shared by the plurality of pixels; and a first separation portion provided in a region surrounded by the element separation wall and separating the plurality of pixels, the first separation portion is provided so as to extend in a thickness direction of the semiconductor substrate, and a first diffusion region containing impurities of a second conductivity type opposite to the first conductivity type is provided in a region positioned around the first separation portion and extending in the thickness direction of the semiconductor substrate.

Abstract: There is provided a solid-state imaging device including: a first semiconductor layer including a photoelectric converter and an electric charge accumulation section for each pixel, the electric charge accumulation section in which a signal electric charge generated in the photoelectric converter is accumulated; a pixel separation section that is provided in the first semiconductor layer, and partitions a plurality of the pixels from each other; a second semiconductor layer that is provided with a pixel transistor and is stacked on the first semiconductor layer, the pixel transistor that reads the signal electric charge of the electric charge accumulation section; and a first shared coupling section that is provided between the second semiconductor layer and the first semiconductor layer, and is provided to straddle the pixel separation section and is electrically coupled to a plurality of the electric charge accumulation sections.

Abstract: A method for controlling a resistive memory device is described. The resistive memory device including a memory cell provided between a first interconnection and a second interconnection crossing the first interconnection, and the memory cell transitions reversibly between a first resistance state and a second resistance state. The method includes detecting a first current flowing through a memory cell by applying a first voltage between the first interconnection and the second interconnection; comparing a value of the first current with a first criteria value; and determining whether the memory cell is in the first resistance state or the second resistance state. The method further includes comparing the value of the first current with a second criteria value greater than the first criteria value; and setting a first flag for the memory cell when the value of the first current is greater than the second criteria value.

Abstract: A method for controlling a resistive memory device is described. The resistive memory device including a memory cell provided between a first interconnection and a second interconnection crossing the first interconnection, and the memory cell transitions reversibly between a first resistance state and a second resistance state. The method includes detecting a first current flowing through a memory cell by applying a first voltage between the first interconnection and the second interconnection; comparing a value of the first current with a first criteria value; and determining whether the memory cell is in the first resistance state or the second resistance state. The method further includes comparing the value of the first current with a second criteria value greater than the first criteria value; and setting a first flag for the memory cell when the value of the first current is greater than the second criteria value.

Abstract: According to an embodiment, an imaging element includes a plurality of light receiving elements, a plurality of scanning circuits, a first line comprising a plurality of nodes, and a plurality of first variable resistance elements. The plurality of scanning circuits are respectively connected to the plurality of light receiving elements. Each of the plurality of first variable resistance elements is connected between the corresponding one of the nodes and a corresponding one of the scanning circuits. At least one of the first variable resistance elements includes a plurality of resistance elements connected to each other in parallel.

Abstract: An integrated circuit according to an embodiment includes: a first wiring line group including at least three first wiring lines; a second wiring line group including second wiring lines; first resistive change elements each including a first and second terminals, and a first resistive change layer; a first select circuit including first input terminals connected to the second wiring lines and a first output terminal, the first select circuit selecting a first input terminal from the first input terminals, and output information from the first output terminal; a third and fourth wiring lines; and a second select circuit selecting two first wiring lines from the first wiring line group, connecting one of the selected two first wiring lines to the third wiring line, and connecting the other one of the selected two first wiring lines to the fourth wiring line.

Abstract: A programmable logic device according to an embodiment includes: a plurality of first and second wiring lines; a plurality of resistive change elements each including a first electrode containing Ni and connected to corresponding one of the first wiring lines, a second electrode containing TiN and connected to corresponding one of the second wiring lines, a resistive change layer containing a hafnium oxide and arranged between the first electrode and the second electrode, and an insulation layer arranged between the resistive change layer and the second electrode, the insulation layer including at least one of an aluminum oxide, an iron oxide, a titanium oxide, a copper oxide, a nickel oxide, a tantalum oxide, a tungsten oxide, a chromium oxide, a rhenium oxide, and a hafnium oxynitride.

Abstract: An integrated circuit according to an embodiment includes: a plurality of first wiring lines; a plurality of second wiring lines intersecting with the plurality of first wiring lines; a plurality of resistive change memory elements provided in cross regions of the plurality of first and second wiring lines, each of which includes a first electrode connected to a corresponding first wiring line, a second electrode connected to a corresponding second wiring line, and a resistive change layer provided between the first and second electrodes, and in each of which a resistive state between the first electrode and the second electrode can be programmed from one of a first resistive state and a second resistive state, which has a larger resistance value than the first resistive state, to the other; and a driver driving the plurality of first and second wiring lines.

Abstract: According to one embodiment, an integrated circuit includes first and second data lines, a first memory cell includes first and second resistance changing elements connected in series between the first and second data lines and a first selection transistor including a drain connected to a connection node of the first and second resistance changing elements, and a second memory cell includes third and fourth resistance changing elements connected in series between the first and second data lines and a second selection transistor including a drain connected to a connection node of the third and fourth resistance changing elements.

Abstract: According to one embodiment, a reconfigurable circuit includes circuit blocks arranged with a matrix of A rows and B columns. Each of the circuit blocks includes M row conductive lines, N column conductive lines crossing the row conductive lines, output inverters each having input and output terminals, the input terminal of each output inverter connected to corresponding one of the row conductive lines, input inverters each having input and output terminals, the output terminal of each input inverter connected to corresponding one of the column conductive lines, and resistance change elements between the row conductive lines and the column conductive lines, each of the resistance change elements including a first terminal and a second terminal, the first terminal being connected to corresponding one of the row conductive lines, the second terminal being connected to corresponding one of the column conductive lines.

Abstract: A look-up table circuit of an embodiment includes: first wiring lines; second wiring lines; resistive change elements disposed to intersection regions of the first and second wiring lines, each resistive change element including a first electrode connected to a corresponding one of the first wiring lines, a second electrode connected to a corresponding one of the second wiring lines; and a resistive change layer disposed between the first electrode and the second electrode; a first controller controlling voltages applied to the first wiring lines; a second controller controlling voltages applied to the second wiring lines; and a multiplexer including input terminals connected to the first wiring lines and an output terminal.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a memory cell including first and second electrodes and a resistance change film therebetween, and a control circuit controlling a potential difference between the first and second electrodes. The control circuit reversibly changes the memory cell to a first resistive state by applying a first potential to the first electrode and by applying a second potential smaller than the first potential to the second electrode. The control circuit reversibly changes the memory cell to a second resistive state by applying a third potential to the first electrode and by applying a fourth potential smaller than the third potential to the second electrode.

Abstract: A semiconductor integrated circuit according to an embodiment includes: N (?1) input wiring lines; M (?1) output wiring lines; N first wiring lines corresponding to the N input wiring lines; K (>M) second wiring lines crossing the N first wiring lines; a plurality of first resistive change elements disposed at intersections of the first wiring lines and the second wiring lines, each of the first resistive change elements including a first electrode connecting to a corresponding one of the first wiring lines, a second electrode connecting to a corresponding one of the second wiring lines, and a first resistive change layer disposed between the first electrode and the second electrode; a first controller controlling a voltage applied to the first wiring lines; a second controller controlling a voltage applied to the second wiring lines; and a selection circuit selecting M second wiring lines from the K second wiring lines.

Abstract: A semiconductor integrated circuit includes: first and second wiring lines; resistive change memories disposed intersection regions of the first and second wiring lines; and a control circuit controlling the first and second drivers to select one of the first wiring lines and one of the second wiring lines, the control circuit changing a resistance of the selected one of the resistive change memories from the first resistive state to the third resistive state, and then changing the resistive state of the selected one of the resistive change memories from the third resistive state to the second resistive state.

Abstract: An integrated circuit according to an embodiment includes: a first wiring line group including at least three first wiring lines; a second wiring line group including second wiring lines; first resistive change elements each including a first and second terminals, and a first resistive change layer; a first select circuit including first input terminals connected to the second wiring lines and a first output terminal, the first select circuit selecting a first input terminal from the first input terminals, and output information from the first output terminal; a third and fourth wiring lines; and a second select circuit selecting two first wiring lines from the first wiring line group, connecting one of the selected two first wiring lines to the third wiring line, and connecting the other one of the selected two first wiring lines to the fourth wiring line.

Abstract: A nonvolatile memory according to an embodiment includes a memory cell, the memory cell including: a memory transistor including a source, a drain, a gate electrode disposed above a channel between the source and the drain, and a gate insulating film disposed between the channel and the gate electrode; and a fuse element disposed between the gate electrode and a wiring line to which the gate electrode of the memory transistor is connected.

Abstract: According to one embodiment, a reconfigurable circuit includes circuit blocks arranged with a matrix of A rows and B columns. Each of the circuit blocks includes M row conductive lines, N column conductive lines crossing the row conductive lines, output inverters each having input and output terminals, the input terminal of each output inverter connected to corresponding one of the row conductive lines, input inverters each having input and output terminals, the output terminal of each input inverter connected to corresponding one of the column conductive lines, and resistance change elements between the row conductive lines and the column conductive lines, each of the resistance change elements including a first terminal and a second terminal, the first terminal being connected to corresponding one of the row conductive lines, the second terminal being connected to corresponding one of the column conductive lines.

Abstract: A programmable logic circuit includes: first to third wiring lines, the second wiring lines intersecting with the first wiring lines; and cells provided in intersecting areas, at least one of cells including a first transistor and a programmable device with a first and second terminals, the first terminal connecting to one of a source and a drain of the first transistor, the second terminal being connected to one of the second wiring lines, the other of the source and the drain being connected to one of the first wiring lines, and a gate of the first transistor being connected to one of the third wiring lines. One of source and drain of each of the first cut-off transistors is connected to the one of the second wiring lines, and an input terminal of each of first CMOS inverters is connected to the other of the source and the drain.

Abstract: A reconfigurable circuit according to an embodiment includes: first wiring lines; second wiring lines crossing the first wiring lines; resistive change elements disposed in intersection regions of the first and second wiring lines, each of the resistive change elements including a first terminal connected to the one of the first wiring lines and a second terminal connected to the one of the second wiring lines, and being switchable between a low-resistance state and a high-resistance state; a first control circuit controlling a voltage to be applied to the first wiring lines; a second control circuit controlling a voltage to be applied to the second wiring lines; and current limiting elements corresponding to the second wiring lines, and controlling current flowing through the resistive change elements connected to the corresponding second wiring line.

Abstract: A semiconductor integrated circuit according to an embodiment includes: N (?1) input wiring lines; M (?1) output wiring lines; N first wiring lines corresponding to the N input wiring lines; K (>M) second wiring lines crossing the N first wiring lines; a plurality of first resistive change elements disposed at intersections of the first wiring lines and the second wiring lines, each of the first resistive change elements including a first electrode connecting to a corresponding one of the first wiring lines, a second electrode connecting to a corresponding one of the second wiring lines, and a first resistive change layer disposed between the first electrode and the second electrode; a first controller controlling a voltage applied to the first wiring lines; a second controller controlling a voltage applied to the second wiring lines; and a selection circuit selecting M second wiring lines from the K second wiring lines.