Patents by Inventor Koji Aoto
Koji Aoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140185860Abstract: A video display method which allows a visible light communication signal to be appropriately transmitted includes: Step SL21 of generating an image having a stripe pattern as a visible light communication image; Step SL22 of calculating average luminance of the visible light communication image; Step SL23 of generating a visible light superimposition image by superimposing the visible light communication image only on, among one or more sub-images included in an image of a video signal that is displayed in the frame, a sub-image that is displayed in a specific sub-frame that is, among one or more sub-frames in each of which a corresponding one of the one or more sub-images is displayed, a sub-frame for representing the average luminance calculated; and Step SL24 of displaying the visible light superimposition image in the specific sub-frame.Type: ApplicationFiled: November 22, 2013Publication date: July 3, 2014Applicant: PANASONIC CORPORATIONInventors: Mitsuaki OSHIMA, Hideki AOYAMA, Koji NAKANISHI, Koji AOTO, Toshiyuki MAEDA, Akira SHIOKAWA, Akihiro UEKI, Takashi SUZUKI
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Publication number: 20140184914Abstract: A video display method in which a visible light communication signal can be appropriately transmitted includes: Step SL 11 of generating a first visible light communication image that is an image having a stripe pattern for visible light communication, by encoding the visible light communication signal; Step SL12 of displaying, in a predetermined frame, an image included in the video signal; and Step SL13 of displaying, in the predetermined frame, the first visible light communication image sequentially thereafter an identification image that is an image having luminance uniformly lower than average luminance of the image that is displayed.Type: ApplicationFiled: November 22, 2013Publication date: July 3, 2014Applicant: PANASONIC CORPORATIONInventors: Mitsuaki OSHIMA, Hideki AOYAMA, Koji NAKANISHI, Koji AOTO, Toshiyuki MAEDA, Akira SHIOKAWA, Akihiro UEKI, Takashi SUZUKI
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Patent number: 8120254Abstract: A plasma display panel (PDP) includes a front panel (2) having a front glass substrate (3) on which display electrodes (6) are formed, a dielectric layer (8) covering the display electrodes (6), and a protective layer (9) formed on the dielectric layer (8). The PDP panel also includes a rear panel (10) facing the front panel (2) to form a discharge space therebetween, and including address electrodes formed along a direction intersecting with the display electrodes (6) and barrier ribs partitioning the discharge space. The protective layer (9) includes a primary film (91) made of MgO and formed on the dielectric layer (8), and aggregated particles (92) formed of several crystal particles of MgO aggregated together and at least one type of particles (93) made of non-organic material and different from aggregated particles (92). The particles (92) and (93) are distributed on the primary film (91).Type: GrantFiled: January 6, 2009Date of Patent: February 21, 2012Assignee: Panasonic CorporationInventors: Koji Aoto, Keiji Horikawa, Kaname Mizokami
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Publication number: 20100327741Abstract: Disclosed is a plasma display panel comprising a front plate (2) wherein a dielectric layer (8) is so formed as to cover a display electrode (6) formed on a front glass substrate (3) and a protective layer (9) is formed on the dielectric layer (8), and a back plate so arranged as to face the front plate (2) so that a discharge space is formed therebetween. The back plate is provided with an address electrode lying in the direction intersecting the display electrode (6) and a partition wall which divides the discharge space. The protective layer (9) is obtained by forming a base film (91) composed of MgO on the dielectric layer (8), and distributing agglomerated particles (92), wherein several MgO crystal particles are agglomerated, and particles (93) of at least one inorganic material, which are different from the agglomerated particles (92), over the base film (91).Type: ApplicationFiled: January 6, 2009Publication date: December 30, 2010Inventors: Koji Aoto, Keiji Horikawa, Kaname Mizokami
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Publication number: 20100314997Abstract: A plasma display panel is formed of front panel (2) and rear panel (10). Front panel (2) includes glass substrate (3) on which display electrodes (6) are formed, dielectric layer (8) covering display electrodes (6), and protective layer (9) formed on dielectric layer (8). Rear panel (10) confronts front panel (2) to form discharge space (16) therebetween, and includes address electrodes (12) formed along a direction intersecting with display electrodes (6), primary dielectric layer (13) covering address electrodes (12), and barrier ribs (14) formed on primary dielectric layer (13) for partitioning discharge space (16). Protective layer (9) includes a primary film made of metal oxide and formed on dielectric layer (8), and an aggregated particle formed of several crystal particles aggregated together and made of metal oxide and attached to the primary film. A percentage of voids of primary dielectric layer (13) falls within a range from 2% to 20%.Type: ApplicationFiled: February 10, 2009Publication date: December 16, 2010Inventors: Keiji Horikawa, Koji Aoto, Kaname Mizokami
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Publication number: 20100187992Abstract: The invention is plasma display panel (1) with a plurality of pairs of display electrodes (6) and dielectric layers (8) disposed on front glass substrate (3), and it is intended to realize plasma display panel (1), wherein the stress at a surface where dielectric layer (8) of front glass substrate (3) is not disposed is a compressive stress ranging from 0.8 MPa to 2.4 MPa, the glass substrate is sufficient in strength, and the panel is almost free from breakage.Type: ApplicationFiled: March 17, 2009Publication date: July 29, 2010Inventors: Koji Akiyama, Masaki Nishinaka, Koji Aoto
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Publication number: 20100176721Abstract: A plasma display panel including rear glass substrate having address electrode, insulating layer, barrier rib and a phosphor layer thereon. Insulating layer does not contain lead. An average value of a void ratio of a region at a depth of up to 50% from rear glass substrate in a thickness of insulating layer ranges from 5% to 15%. A plasma display panel having a long lifetime and high productivity is achieved.Type: ApplicationFiled: April 1, 2009Publication date: July 15, 2010Inventors: Ken Hasegawa, Keisuke Sumida, Morio Fujitani, Kenichi Kusaka, Hideyuki Shirahase, Kohshiroh Mizuno, Koji Aoto, Keiji Horikawa
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Publication number: 20100171420Abstract: A plasma display panel has a plurality of pairs of display electrodes, dielectric layer, and protective layer disposed on front glass substrate. Protective layer is formed of nano crystal particles, and the average particle diameter of the nano crystal particles is in the range of 10 nm to 100 nm. With this structure, in the plasma display panel, front glass substrate has a sufficient strength and occurrence of panel cracks is reduced.Type: ApplicationFiled: March 25, 2009Publication date: July 8, 2010Inventors: Koji Akiyama, Koji Aoto, Masaki Nishimura, Masaki Nishinaka
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Patent number: 7629947Abstract: Disclosed here is a method of aging a plasma display panel. The aging method of the present invention contains a first aging period and a second aging period. In the first aging period, applying voltage Vd1 to at least any one of the scan electrodes, the sustain electrodes, and the address electrodes suppress self-erase discharge that occurs in the wake of aging voltage generated by application of voltage in which the scan electrodes take a voltage level higher than the sustain electrodes. In the second aging period, applying voltage Vd2 to at least any one of the scan electrodes, the sustain electrodes, and the address electrodes suppress self-erase discharge that occurs in the wake of aging voltage generated by application of voltage in which the sustain electrodes take a voltage level higher than the scan electrodes. The above aging method offers a power-efficient aging process with the aging time accelerated.Type: GrantFiled: May 24, 2005Date of Patent: December 8, 2009Assignee: Panasonic CorporationInventors: Koji Akiyama, Masaaki Yamauchi, Takashi Aoki, Koji Aoto
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Patent number: 7288012Abstract: A plasma display panel is provided that includes scan electrodes, sustain electrodes, and address electrodes. A first pulse voltage for the address electrodes or a second pulse voltage for the address electrodes is applied to the address electrodes in an aging step in which aging discharge is performed by alternately applying pulse voltage for the scan electrodes and pulse voltage for the sustain electrodes at least across the scan electrodes and the sustain electrodes. The first pulse voltage has a rising edge timing synchronized with a rising edge timing of the pulse voltage for the scan electrodes and a pulse width smaller than that of the pulse voltage for the scan electrodes. The second pulse voltage has a rising edge timing synchronized with a rising edge timing of the pulse voltage for the sustain electrodes and a pulse width smaller than that of the pulse voltage for the sustain electrodes.Type: GrantFiled: June 17, 2004Date of Patent: October 30, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koji Akiyama, Koji Aoto, Masaaki Yamauchi, Takashi Aoki, Akihiro Matsuda
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Patent number: 7207858Abstract: Disclosed is a method of manufacturing plasma display panels for carrying out aging with high productivity. In an aging process for applying a predetermined voltage and driving plasma display panels 21 for display operation, each plasma display panel is set into an aging unit provided with cooling means, and the aging is carried out on the plasma display panel while cooling the plasma display panel by the cooling means provided in the aging unit. This method can thus reduce temperature rise of the panel and prevent the panel from being cracked during the aging process.Type: GrantFiled: April 2, 2003Date of Patent: April 24, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiro Matsuda, Fumio Sakamoto, Kenji Date, Koji Aoto
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Patent number: 7175493Abstract: A plasma display panel capable of realizing improvement in the characteristics thereof, such as lower discharge voltage, more stable discharge, higher luminance, higher efficiency, and longer life. During a step of sealing the periphery of substrates or before this sealing step, impurity gas other then inert gas is adsorbed by phosphor layers. The impurity gas is released into discharge gas and the impurity is added to the discharge gas in a controlled manner while the panel is lit. This method can realize improvement in characteristics, such as lower discharge voltage, higher luminance, higher efficiency, and longer life.Type: GrantFiled: March 30, 2005Date of Patent: February 13, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masaki Nishimura, Koji Akiyama, Kanako Miyashita, Koji Aoto, Keiji Horikawa, Masaaki Yamauchi
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Publication number: 20060284795Abstract: Disclosed here is a method of aging a plasma display panel. The aging method of the present invention contains a first aging period and a second aging period. In the first aging period, applying voltage Vd1 to at least any one of the scan electrodes, the sustain electrodes, and the address electrodes suppress self-erase discharge that occurs in the wake of aging voltage generated by application of voltage in which the scan electrodes take a voltage level higher than the sustain electrodes. In the second aging period, applying voltage Vd2 to at least any one of the scan electrodes, the sustain electrodes, and the address electrodes suppress self-erase discharge that occurs in the wake of aging voltage generated by application of voltage in which the sustain electrodes take a voltage level higher than the scan electrodes. The above aging method offers a power-efficient aging process with the aging time accelerated.Type: ApplicationFiled: May 24, 2005Publication date: December 21, 2006Inventors: Koji Akiyama, Masaaki Yamauchi, Takashi Aoki, Koji Aoto
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Publication number: 20060228972Abstract: An aging method and an aging device are provided by which a plasma display panel that reduces the generation of irregular color and that has a high display quality can be obtained. An aging method and an aging apparatus for plasma display panels are disclosed which enable to obtain a plasma display panel with high display quality wherein color irregularities are suppressed. The aging apparatus for plasma display panels comprises a plurality of fans. When air is blown to a plasma display panel using the fans during aging of the plasma display panel, at least the direction or the amount of air blow by at least one of the fans is changed so that the temperatures of image display regions in the plasma display panel can be uniform, thereby suppressing color irregularities.Type: ApplicationFiled: July 16, 2004Publication date: October 12, 2006Inventors: Koji Akiyama, Koji Aoto, Masaaki Yamauchi, Takashi Aoki
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Publication number: 20060166585Abstract: In a plasma display panel including scan electrodes, sustain electrodes, and address electrodes, first pulse voltage for the address electrodes or second pulse voltage for the address electrodes is applied to the address electrodes, in an aging step in which aging discharge is performed by alternately applying pulse voltage for the scan electrodes and pulse voltage for the sustain electrodes at least across the scan electrodes and the sustain electrodes. The first pulse voltage has rising edge timing synchronizing with rising edge timing of the pulse voltage for the scan electrodes and a pulse width smaller than that of the pulse voltage for the scan electrodes. The second pulse voltage has rising edge timing synchronizing with rising edge timing of the pulse voltage for the sustain electrodes and a pulse width smaller than that of the pulse voltage for the sustain electrodes.Type: ApplicationFiled: June 17, 2004Publication date: July 27, 2006Inventors: Koji Akiyama, Koji Aoto, Masaaki Yamauchi, Takashi Aoki, Akihiro Matsuda
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Patent number: 7037156Abstract: A plasma display panel capable of realizing improvement in the characteristics thereof, such as lower discharge voltage, more stable discharge, higher luminance, higher efficiency, and longer life. Before a step of sealing the periphery of substrates, impurity gas containing CO2, H2O and CH4 is other then inert gas is adsorbed by phosphor layers. The impurity gas is released into discharge gas and while the panel is lit. This method can realize improvement in characteristics, such as lower discharge voltage, higher luminance, higher efficiency, and longer life.Type: GrantFiled: December 20, 2002Date of Patent: May 2, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masaki Nishimura, Koji Akiyama, Kanako Miyashita, Koji Aoto, Keiji Horikawa, Masaaki Yamauchi
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Publication number: 20050168126Abstract: A plasma display panel capable of realizing improvement in the characteristics thereof, such as lower discharge voltage, more stable discharge, higher luminance, higher efficiency, and longer life. During a step of sealing the periphery of substrates or before this sealing step, impurity gas other then inert gas is adsorbed by phosphor layers. The impurity gas is released into discharge gas and the impurity is added to the discharge gas in a controlled manner while the panel is lit. This method can realize improvement in characteristics, such as lower discharge voltage, higher luminance, higher efficiency, and longer life.Type: ApplicationFiled: March 30, 2005Publication date: August 4, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Masaki Nishimura, Koji Akiyama, Kanako Miyashita, Koji Aoto, Keiji Horikawa, Masaaki Yamauchi
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Publication number: 20040242110Abstract: Disclosed is a method of manufacturing plasma display panels for carrying out aging with high productivity. In an aging process for applying a predetermined voltage and driving plasma display panels 21 for display operation, each plasma display panel is set into an aging unit provided with cooling means, and the aging is carried out on the plasma display panel while cooling the plasma display panel by the cooling means provided in the aging unit. This method can thus reduce temperature rise of the panel and prevent the panel from being cracked during the aging process.Type: ApplicationFiled: January 30, 2004Publication date: December 2, 2004Inventors: Akihiro Matsuda, Fumio Sakamoto, Kenji Date, Koji Aoto
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Patent number: 6768478Abstract: The object of the present invention is to provide a method of driving of an AC type plasma display panel with higher emitting efficiency without increasing the external-sustain voltage VSUS, even if the discharge sustain gap dp is extended. An AC type plasma display panel according to the present invention comprises a first and second substrates arranged opposite to each other. The first substrate includes a plurality pairs of a first and second electrodes extending parallel each other, and a dielectric layer covering thereon. The second substrate includes a plurality of third electrodes extending in a direction crossing the first and second electrodes, and a plurality of partition walls between each third electrode. A method of the panel according to the present invention comprises applying a voltage so that the discharge generated in the first opposing discharge space progresses towards a second opposing discharge space and extends along the third electrode.Type: GrantFiled: September 27, 2000Date of Patent: July 27, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koichi Wani, Kazunori Hirao, Koji Aoto, Yoshihito Tahara
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Publication number: 20040135506Abstract: A plasma display panel capable of realizing improvement in the characteristics thereof, such as lower discharge voltage, more stable discharge, higher luminance, higher efficiency, and longer life. During a step of sealing the periphery of substrates or before this sealing step, impurity gas other then inert gas is adsorbed by phosphor layers. The impurity gas is released into discharge gas and the impurity is added to the discharge gas in a controlled manner while the panel is lit. This method can realize improvement in characteristics, such as lower discharge voltage, higher luminance, higher efficiency, and longer life.Type: ApplicationFiled: September 4, 2003Publication date: July 15, 2004Inventors: Masaki Nishimura, Koji Akiyama, Kanako Miyashita, Koji Aoto, Keiji Horikawa, Masaaki Yamauchi