Abstract: This invention achieves lower electric power consumption of a sensor node for carrying out an intermittent operation, in a sensor net system. A time when the sensor node transmits a signal to a base station is estimated. Then, in accordance with the estimation, a table for storing a signal transmitted from the sensor node is installed in a wireless section of the base station. Consequently, a communication time between the sensor node and the base station can be made shorter. Also, a start time of a micro computer is set for RTC inside the sensor node, so the micro computer inside the sensor node can be put in the standby state.

Abstract: A computer readable medium is arranged to record a circuit description having a description of a function of the circuit module and an interface description provided by distinguishing sets of possible signal values each output terminal may take on plural time points at each pattern and adding an identifier to each of said sets for defining said set and representing said function of said hardware description with the set of said identifiers on a temporal order.

Abstract: According to the disclosed invention, an index for evaluating an IP objectively and quantitatively is set so that users will refer to the index as the criterion for looking for an IP providing user-desired function. IP vendors prepare a higher-level index of verification range that is separated into infinite degrees than the existing indexes of verification range such as hardware source code coverage and path coverage. According to this index, what extent or degree to which IP functionality has been verified is determined. The thus determined degree of verification is expressed by a validation level that is added to IP information to be provided to users.

Abstract: A storage medium readable by a computer for storing a circuit module's interface information, a connection-verifying method for determining whether or not a first circuit module can be connected to a second circuit module and a presentation method for a circuit module's interface information, utilize the interface information comprising high-level combinations, each combination including first identifier sets and second identifier sets, wherein each of the first identifier sets is a combination pattern of values of signals, each signal appearing at a predetermined time at one of ports pertaining to a first port set of the circuit module, and wherein each of the second identifier sets is a combination pattern of values of signals, each signal appearing at a predetermined time at one of ports pertaining to a second port set of the circuit module.

Abstract: Information of definitions on interface specifications capable of expressing parallel behaviors is stored in a computer-readable storage medium while amounts of information are reduced. The present invention comprises: a first identifier region for storing, as a first set of ports, combination patterns of signal values that respective ports of a first set of ports are capable of assuming; a second identifier region for storing, as a second set of ports, combination patterns of signal values that respective ports of a second set of ports are capable of assuming; and a third identifier region for storing, as a third set of ports, functions of a circuit module defined as combinations of first identifiers and second identifiers, wherein the third identifiers include codes (par) indicating that starting order of combination patterns corresponding to the first identifiers and combination patterns corresponding to the second identifiers are undefined.

Abstract: A computer readable medium is arranged to record a circuit description having a description of a function of the circuit module and an interface description provided by distinguishing sets of possible signal values each output terminal may take on plural time points at each pattern and adding an identifier to each of said sets for defining said set and representing said function of said hardware description with the set of said identifiers on a temporal order.

Abstract: According to the disclosed invention, an index for evaluating an IP objectively and quantitatively is set so that users will refer to the index as the criterion for looking for an IP providing user-desired function. IP vendors prepare a higher-level index of verification range that is separated into infinite degrees than the existing indexes of verification range such as hardware source code coverage and path coverage. According to this index, what extent or degree to which IP functionality has been verified is determined. The thus determined degree of verification is expressed by a validation level that is added to IP information to be provided to users.

Abstract: A computer readable medium is arranged to record a circuit description having a description of a function of the circuit module and an interface description provided by distinguishing sets of possible signal values each output terminal may take on plural time points at each pattern and adding an identifier to each of said sets for defining said set and representing said function of said hardware description with the set of said identifiers on a temporal order.

Abstract: A storage medium readable by a computer is used for storing a circuit module's interface information having high-level combinations each including first identifier sets and second identifier sets where: