Abstract: A system including a device with a first chip and a device with a second chip, to realize contactless communication therebetween. The first chip includes a transmitter circuit converting parallel data into a differential signal and a transmitting antenna transmitting the signal to the second chip. The second chip includes a receiving antenna receiving the differential signal from the transmitting antenna and a receiver circuit converting the differential signal into the parallel data. The transmitting and receiving antenna each include at least two antenna elements, first and second terminals, and first and second junctions. The antenna elements consist of wiring lines on the chips. The terminals are connected with circuits on the chips. At the first junction, first ends of the antenna elements meet to connect to the first terminal. At the second junction, second ends of the antenna elements meet to connect to the second terminal.

Abstract: The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.

Abstract: Provided is a hierarchical arbitration device wherein an arbitration device at each level of the hierarchy selects a resource use request having the highest priority and a resource use request having the second highest priority, outputting these two resource use requests to the arbitration device that is one level higher. After outputting the memory use request having the highest priority to a resource control unit as the top priority resource use request, when the arbitration device at the highest level of the hierarchy receives a signal from the memory control unit indicating receipt of the resource use request, the arbitration device then selects the resource use request having the second highest priority and outputs this resource request as the next top priority resource use request.

Abstract: A memory access control unit is provided with a storage unit for storing a page table that stores a correspondence between a piece of data, a virtual page number, and a physical page number for all pages, and a conversion unit that includes a buffer for storing, for each of a subset of the pages, the virtual page number and the physical page number in correspondence, and a conversion processing unit operable to convert a virtual address into a physical address in accordance with content stored in the buffer.

Abstract: An access control apparatus receives access requests from one or more regular masters and an irregular master and sequentially selects an access allowable target. Additionally, the access control apparatus calculates an amount of unused resources based on an amount of resources used by a regular master and a maximum amount of resources to be used by the regular master, and manages the unused resources. The access control apparatus selects an access request of an irregular master as an access allowable target when the irregular master makes the access request during a unit period and access based on an access request of at least one of the regular masters that has not been executed. The managed amount of unused resources is equal to or larger than an amount of resources which is to be used based on the access request of the irregular master.

Abstract: In order to realize efficient memory access by reducing frequency at which areas specified by different row addresses in the same bank in a memory are consecutively accessed, the data processing apparatus (10) performs mapping so as to store data (21) and data (22), which are the same data, with use of the first arrangement and the second arrangement, respectively, in different memory areas constituting a memory (20). When reading a portion of the data, a selecting unit (21) selects one of the arrangements that is more efficient in accessing the portion of the data based on an address range corresponding to the portion of the data according to each arrangement, and an access control unit (13) accesses a memory area corresponding to the selected arrangement. Here, the data (21) is mapped to a position different from a position of the data (22) in terms of relative positions with respect to boundary addresses of blocks each corresponding to the same row address in the same bank.

Abstract: The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.

Abstract: The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.

Abstract: A memory access control unit is provided with a storage unit for storing a page table that stores a correspondence between a piece of data, a virtual page number, and a physical page number for all pages, and a conversion unit that includes a buffer for storing, for each of a subset of the pages, the virtual page number and the physical page number in correspondence, and a conversion processing unit operable to convert a virtual address into a physical address in accordance with content stored in the buffer.

Abstract: Provided is a hierarchical arbitration device wherein an arbitration device at each level of the hierarchy selects a resource use request having the highest priority and a resource use request having the second highest priority, outputting these two resource use requests to the arbitration device that is one level higher. After outputting the memory use request having the highest priority to a resource control unit as the top priority resource use request, when the arbitration device at the highest level of the hierarchy receives a signal from the memory control unit indicating receipt of the resource use request, the arbitration device then selects the resource use request having the second highest priority and outputs this resource request as the next top priority resource use request.

Abstract: A memory controller (101) according to this invention includes: a command generation unit (102) which generates access commands each including a physical address, based on an access request including a logical address indicating a rectangular area in image data; and a command issuance unit (105) which issues, to a memory (0), the access commands generated by the command generation unit (102). The command generation unit (102) includes a group determination unit (104) which determines a group to which a bank including data to be accessed belongs, based on the physical address corresponding to the access request. The command generation unit (102) generates a pair of a first and a second access commands which share a prefetch buffer between two banks belonging to different groups, when data to be accessed is continuous across two banks belonging to different groups.

Abstract: The present invention aims to provide an access control apparatus that can improve responsiveness to an access request of a processor compared with a conventional technology. The access control apparatus, which receives access requests from one or more regular masters and a irregular master and sequentially selects an access allowable target, calculates an amount of unused resources based on an amount of resources used by a regular master which makes an access request during a unit period and a maximum amount of resources to be used given to the regular master and manages it.

Abstract: A semiconductor integrated circuit ensures to reserve a required memory bandwidth at low cost. A memory bandwidth monitoring unit 1210 calculates a required memory bandwidth, monitors the usage condition of the memory, and outputs the following information to a reconfiguration control unit 1120. The information is necessary to reconfigure a reconfiguration unit 1110 into a logic unit and a temporary buffer both of which are scalable depending on the usage condition. According to information, the reconfiguration control unit 1120 controls the reconfiguration unit 1110. The buffer is for storing data accessed to or from the memory by each bus master. The logic unit acts as a bus master that only uses a portion of the memory bandwidth that remains unused during the time no access request to the data storage unit 1002 issued by a bus master unit having a higher priority level is being executed.

Abstract: The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.

Abstract: The present invention provides a reconfigurable circuit that comprises a plurality of reconfiguration cells and changes a configuration of a computation processing unit included in each of the reconfiguration cells. Here, each of the reconfiguration cells further includes: a computation storage unit operable to store a result of a computation performed by the computation processing unit; a flag holding unit operable to hold an initialization flag indicating whether an initialization of the computation storage unit is required; and an initialization control unit operable to, during the configuration change of the computation processing unit, control the initialization of the computation storage unit based on the initialization flag held by the flag holding unit.

Abstract: Technology is disclosed that allows a viewer to estimate the value of unknown content, and pay a fee relative to the estimated value. A cost corresponding to the value of each section is output for each of a plurality of sections that compose the received content. The recipient estimates the value of each section by referencing the cost of each section. Accordingly, the balance between the value and price of the section viewed on a trial basis does not produce a situation markedly different from that anticipated by the recipient, thus preventing dissatisfaction relating to the cost of the section viewed on a trial basis. A benefit is that, since the recipient views the section on a trial basis while having anticipated the value of the section, the recipient is more inclined to trial view unknown content, and the recipient can be expected to view more content by the content producer.

Abstract: Monohydrate and trihydrate crystals of N-(2-(4-(5H-dibenzo[a,d]cyclohepten-5-ylidene)-piperidino) ethyl)-1-formyl-4-piperidinecarboxamide hydrochloride having excellent stability.

Abstract: Monohydrate and trihydrate crystals of N-(2-(4-(5H-dibenzo[a,d]cyclohepten-5-ylidene)-piperidino) ethyl)-1-formyl-4-piperidinecarboxamide hydrochloride having excellent stability.

Abstract: Monohydrate and trihydrate crystals of N-(2-(4-(5H-dibenzo[a,d]cyclohepten-5-ylidene)-piperidino) ethyl)-1-formyl-4-piperidinecarboxamide hydrochloride having excellent stability.

Abstract: Monohydrate and trihydrate crystals of N-(2-(4-(5H dibenzo [a,d]cyclohepten-5-ylidene)-piperidino)ethyl)-1-formyl-4-piperidinecarboxamide hydrochloride having excellent stability.