Abstract: A cell culture equipment comprising a culture component permeable member 10 that is permeable to culture components, a culture vessel 30 that covers one side of the culture component permeable member 10 and holds a cell-containing medium, and a medium holding vessel 40 that covers the other side of the culture component permeable member 10 and holds a medium.

Abstract: Disclosed herein is a semiconductor memory device, including: a memory array section wherein a memory array which requires a refresh operation is formed; an interface section configured to carry out an interfacing process between an external apparatus and the memory array section; and a refresh control block for controlling the refresh operation; the interface section configured to include a plurality of interface modules individually corresponding to a plurality of memory types and selectively applied to the interfacing process between the external apparatus and the memory array section; the refresh control block having a function of issuing a refresh command within a refresh cycle and another function of preventing, if, upon issuance of the refresh command, an access command and the refresh command to the memory array are estimated to collide with each other, the collision.

Abstract: Disclosed herein is a semiconductor memory device, including: a memory array section wherein a memory array which is accessed with a predetermined data bus width is formed; an interface section configured to carry out interfacing between an external apparatus and the memory array section; and a converter having a conversion function of data and a control signal between the interface section and the memory array section and having conversion functions corresponding to specifications of the memory array; the interface section including a plurality of interface modules individually corresponding to different memory types and selectively adapted for the interfacing process between the external apparatus and the memory array section; the converter having a data width variation function of issuing a command and an address for the memory array based on information of access data of the memory array and outputting the access data after varying or without varying the data width.

Abstract: It is an object of the invention to provide an address generating circuit for data compression capable of generating addresses in accordance with address compression blocks from any address in a failure analysis memory by executing an operation of the compression rate to an address compression block end by a CPU based on a start address position and an address compression rate. At an address generation starting time, a start address data b is held by a flip flop 3B and it is loaded at the same time into an up counter 5B as an output of a selector 4B, so that address generating operation is performed by a single clock.