Patents by Inventor Koji Ebara

Koji Ebara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220146444
    Abstract: A method for measuring a resistivity of a silicon single crystal by a four-point probe method including: a first grinding step of grinding at a surface of the silicon single crystal on which the resistivity is measured; a cleaning step of cleaning the silicon single crystal subjected to the first grinding step; a donor-annihilation heat treatment step of heat-treating the silicon single crystal subjected to the cleaning step; and a second grinding step of grinding at least the surface of the silicon single crystal subjected to the donor-annihilation heat treatment step on which the resistivity is to be measured, where the resistivity of the silicon single crystal is measured by the four-point probe method after performing the second grinding step. This provides a method for measuring a resistivity of a silicon single crystal by which stable measurement is possible over a long period of time after a donor-annihilation heat treatment.
    Type: Application
    Filed: January 27, 2020
    Publication date: May 12, 2022
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Fumitaka KUME, Yukari SUZUKI, Koichi KITAMURA, Masahiro YOSHIDA, Shuji YOKOTA, Koji EBARA
  • Patent number: 10297463
    Abstract: A method for manufacturing a silicon wafer having a denuded zone in a surface layer by performing a heat treatment to a silicon wafer, including: a step A, performing a first rapid heat treatment of 0.01 msec or more and 100 msec or less to an upper surface layer alone of the silicon wafer to be treated at 1300° C. or more and a silicon melting point or less by using a first heat source which heats the silicon wafer to be treated from above; and a step B, holding the silicon wafer to be treated at 1100° C. or more and less than 1300° C. for one second or more and 100 seconds or less by a second rapid heat treatment using a second heat source which heats the silicon wafer to be heated, and decreasing the temperature at a falling rate of 30° C./sec or more and 150° C./sec or less.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: May 21, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Katsuyoshi Suzuki, Hiroshi Takeno, Koji Ebara
  • Publication number: 20180247830
    Abstract: A method for manufacturing a silicon wafer having a denuded zone in a surface layer by performing a heat treatment to a silicon wafer, including: a step A, performing a first rapid heat treatment of 0.01 msec or more and 100 msec or less to an upper surface layer alone of the silicon wafer to be treated at 1300° C. or more and a silicon melting point or less by using a first heat source which heats the silicon wafer to be treated from above; and a step B, holding the silicon wafer to be treated at 1100° C. or more and less than 1300° C. for one second or more and 100 seconds or less by a second rapid heat treatment using a second heat source which heats the silicon wafer to be heated, and decreasing the temperature at a falling rate of 30° C./sec or more and 150° C./sec or less.
    Type: Application
    Filed: January 7, 2016
    Publication date: August 30, 2018
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Katsuyoshi SUZUKI, Hiroshi TAKENO, Koji EBARA
  • Patent number: 9390905
    Abstract: A method for manufacturing a silicon substrate, including: performing a rapid heat treatment to a silicon substrate with a rapid-heating and rapid-cooling apparatus by maintaining the silicon substrate at a temperature that is higher than 1300° C. and not greater than a silicon melting point for 1 to 60 seconds, the silicon substrate being sliced from a silicon single crystal ingot grown by the Czochralski method; performing a first temperature decrease process down to a temperature in the range of 600 to 800° C. at a temperature decrease rate of 5 to 150° C./sec; and performing a second temperature decrease process in such a manner that a cooling time of X seconds and a temperature decrease rate of Y° C./sec meet Y?0.15X-4.5 when X<100 and meet Y?10 when X?100.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: July 12, 2016
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tetsuya Oka, Koji Ebara, Shuji Takahashi
  • Patent number: 9252025
    Abstract: According to the present invention, there is provided a method for manufacturing a silicon single crystal wafer, wherein a first heat treatment for holding a silicon single crystal wafer in an oxygen containing atmosphere at a first heat treatment temperature for 1 to 60 seconds and cooling it to 800° C. or less at a temperature falling rate of 1 to 100° C./second by using a rapid heating/rapid cooling apparatus is performed to inwardly diffuse oxygen and form an oxygen concentration peak region near a surface of the silicon single crystal wafer, and then a second heat treatment is performed to agglomerate oxygen in the silicon single crystal wafer into the oxygen concentration peak region. As a result, it is possible to provide the method for manufacturing a silicon single crystal wafer that enables forming an excellent gettering layer close to a device forming region.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: February 2, 2016
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tetsuya Oka, Koji Ebara
  • Publication number: 20150001680
    Abstract: According to the present invention, there is provided a method for manufacturing a silicon single crystal wafer, wherein a first heat treatment for holding a silicon single crystal wafer in an oxygen containing atmosphere at a first heat treatment temperature for 1 to 60 seconds and cooling it to 800° C. or less at a temperature falling rate of 1 to 100° C./second by using a rapid heating/rapid cooling apparatus is performed to inwardly diffuse oxygen and form an oxygen concentration peak region near a surface of the silicon single crystal wafer, and then a second heat treatment is performed to agglomerate oxygen in the silicon single crystal wafer into the oxygen concentration peak region. As a result, it is possible to provide the method for manufacturing a silicon single crystal wafer that enables forming an excellent gettering layer close to a device forming region.
    Type: Application
    Filed: December 14, 2012
    Publication date: January 1, 2015
    Inventors: Tetsuya Oka, Koji Ebara
  • Publication number: 20130316139
    Abstract: A method for manufacturing a silicon substrate, including: performing a rapid heat treatment to a silicon substrate with a rapid-heating and rapid-cooling apparatus by maintaining the silicon substrate at a temperature that is higher than 1300° C. and not greater than a silicon melting point for 1 to 60 seconds, the silicon substrate being sliced from a silicon single crystal ingot grown by the Czochralski method; performing a first temperature decrease process down to a temperature in the range of 600 to 800° C. at a temperature decrease rate of 5 to 150° C./sec; and performing a second temperature decrease process in such a mariner that a cooling time of X seconds and a temperature decrease rate of Y° C./sec meet Y?0.15X?4.5 when X<100 and meet Y?10 when X?100.
    Type: Application
    Filed: February 2, 2012
    Publication date: November 28, 2013
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tetsuya Oka, Koji Ebara, Shuji Takahashi
  • Publication number: 20130098888
    Abstract: The present invention is a method for heat-treating a wafer, the method by which heat treatment at a predetermined temperature with rapid rise and fall of temperature is performed by performing heating by a heating source in a state in which a principal surface (a first principal surface) of a wafer is supported by a supporting member, the method in which heat treatment is performed with control of the heating source being performed in such a way that the temperature of the first principal surface supported by the supporting member becomes 1 to 25° C. higher than the temperature of a principal surface (a second principal surface) opposite to the first principal surface of the wafer. As a result, a method for heat-treating a wafer, the method that can reliably suppress a slip dislocation generated from a wafer supporting position when heat treatment is performed on a silicon wafer, is provided.
    Type: Application
    Filed: July 15, 2011
    Publication date: April 25, 2013
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Koji Ebara, Tetsuya Oka, Shuji Takahashi
  • Publication number: 20130093060
    Abstract: A silicon wafer and method for producing a silicon wafer, including at least: a first heat treatment process in which rapid heat treatment is performed on the wafer by using a rapid heating/cooling apparatus in an atmosphere containing at least one of nitride film formation atmospheric gas, rare gas, and oxidizing gas at a temperature higher than 1300° C. and lower than or equal to a silicon melting point for 1 to 60 seconds; and a second heat treatment process in which temperature and atmosphere are controlled to suppress generation of a defect caused by a vacancy in the wafer and rapid heat treatment is performed on the wafer. Therefore, RIE defects such as oxide precipitates, COPs, and OSFs are not present at a depth of at least 1 ?m from the surface, which becomes a device fabrication region, and the lifetime is 500 ?sec or longer.
    Type: Application
    Filed: June 7, 2011
    Publication date: April 18, 2013
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tetsuya Oka, Koji Ebara, Shuji Takahashi
  • Patent number: 8377202
    Abstract: A method for manufacturing a silicon wafer having a defect-free region in a surface layer, in which at least only a surface layer region to a predetermined depth from a front surface of a silicon wafer to be processed is subjected to heat treatment at a temperature of not less than 1100 degrees C. for not less than 0.01 msec to not more than 1 sec, to thereby make the surface layer defect-free. As a result of this, there is provided a method for manufacturing a silicon wafer, in which a DZ layer without generation of crystal defects from the front surface to a constant depth can be uniformly formed, and oxide precipitates having a steep profile inside the wafer can be secured and controlled with a high degree of accuracy.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: February 19, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Koji Ebara
  • Publication number: 20120001301
    Abstract: An annealed wafer obtained by performing rapid thermal annealing on a silicon single crystal wafer sliced from a silicon single crystal ingot in which an entire plane is an OSF region, an N region outside an OSF region, or a mixed region thereof, the silicon single crystal ingot being grown by the Czochralski method, in which RIE defects do not exist in a region having at least a depth of 1 ?m from a surface, a good chip yield of a TDDB characteristic is 80% or more, and a depth of a region where an oxygen concentration is decreased due to outward diffusion is within 3 ?m from the surface, and a method for producing an annealed wafer.
    Type: Application
    Filed: March 17, 2010
    Publication date: January 5, 2012
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Koji Ebara, Yoshinori Hayamizu, Hiroyasu Kikuchi
  • Publication number: 20110001219
    Abstract: The present invention is a silicon single crystal wafer grown by the Czochralski method, the silicon single crystal wafer in which an wafer entire plane is an N region located outside OSFs which are generated in the form of a ring when thermal oxidation treatment is performed and contains no defect region detected by the RIE process. As a result, a silicon single crystal wafer which belongs to none of a vacancy-rich V region, an OSF region, a Dn region in an Nv region, the Dn region in which a defect detected by the Cu deposition process is generated, and an interstitial silicon-rich I region and can improve the TDDB characteristic which is the time dependent breakdown characteristic of an oxide film more reliably than a known silicon single crystal wafer is provided, and the silicon single crystal wafer is provided under stable production conditions.
    Type: Application
    Filed: February 19, 2009
    Publication date: January 6, 2011
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventors: Koji Ebara, Shizuo Igawa, Tetsuya Oka
  • Patent number: 7839426
    Abstract: A time recorder includes a print head, a ribbon cassette swingably supported and having an ink ribbon applied with a different colors in a width direction, and a cam for swinging the ribbon cassette to change a position of the ink ribbon against the print head in the width direction of the ink ribbon and to change a color to be printed on time card, further comprising a first stopper and a second stopper for limiting a rotational range of the cam.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: November 23, 2010
    Assignee: Seiko Precision Inc.
    Inventor: Koji Ebara
  • Publication number: 20090242843
    Abstract: A method for manufacturing a silicon wafer having a defect-free region in a surface layer, in which at least only a surface layer region to a predetermined depth from a front surface of a silicon wafer to be processed is subjected to heat treatment at a temperature of not less than 1100 degrees C. for not less than 0.01 msec to not more than 1 sec, to thereby make the surface layer defect-free. As a result of this, there is provided a method for manufacturing a silicon wafer, in which a DZ layer without generation of crystal defects from the front surface to a constant depth can be uniformly formed, and oxide precipitates having a steep profile inside the wafer can be secured and controlled with a high degree of accuracy.
    Type: Application
    Filed: May 17, 2007
    Publication date: October 1, 2009
    Applicant: SHIN-ETSU HANDOTAI CO., LTD
    Inventor: Koji Ebara
  • Publication number: 20090109249
    Abstract: A time recorder includes a print head, a ribbon cassette swingably supported and having an ink ribbon applied with a different colors in a width direction, and a cam for swinging the ribbon cassette to change a position of the ink ribbon against the print head in the width direction of the ink ribbon and to change a color to be printed on time card, further comprising a first stopper and a second stopper for limiting a rotational range of the cam.
    Type: Application
    Filed: December 22, 2008
    Publication date: April 30, 2009
    Applicant: SEIKO PRECISION INC.
    Inventor: Koji EBARA
  • Publication number: 20090007839
    Abstract: The present invention provides a method for manufacturing a silicon single crystal wafer in which a silicon single crystal ingot is pulled by a CZ method, and a wafer sliced from the ingot is subjected to a rapid thermal annealing, wherein wafers sliced from the ingot which has been pulled while changing a pulling rate are subjected to rapid thermal annealings in various heat treatment temperatures, oxide dielectric breakdown voltage measurements are performed to get a relation between the pulling rate and the heat treatment temperatures, and a result of the oxide dielectric breakdown voltage measurements in advance, conditions of a pulling rate and a heat treatment temperature are determined based on the relation so that the whole area thereof in the radial direction may become N region after the rapid thermal annealing, and the pulling of the ingot and the rapid thermal annealing are performed to thereby manufacture the silicon single crystal wafer.
    Type: Application
    Filed: December 21, 2006
    Publication date: January 8, 2009
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventor: Koji Ebara
  • Publication number: 20090000535
    Abstract: The present invention provides a method for manufacturing a silicon single crystal wafer by which a silicon single crystal ingot is pulled based on a Czochralski method and a rapid thermal annealing is performed with respect to a wafer that is sliced out from the silicon single crystal ingot and has a whole area in a radial direction formed of N region, wherein a heat treatment at 800 to 1100° C. as a heat treatment temperature for two hours or below as a hear treatment time is carried out after the rapid thermal annealing while adjusting the heat treatment temperature and the heat treatment time so that at least diffusion distances of vacancies as point defects injected by the rapid thermal annealing become longer than diffusion distances of the vacancies by a heat treatment performed at 800° C. for 30 minutes, thereby annihilating a vacancy type defect.
    Type: Application
    Filed: December 21, 2006
    Publication date: January 1, 2009
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventor: Koji Ebara
  • Patent number: 6914442
    Abstract: The present invention is to provide a method for measuring resistivity of a semiconductor wafer by the use of an AC-SPV method even though the wafer is left in a depletion state or a weak inversion state.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: July 5, 2005
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Koji Ebara
  • Publication number: 20040212377
    Abstract: The present invention is to provide a method for measuring resistivity of a semiconductor wafer by the use of an AC-SPV method even though the wafer is left in a depletion state or a weak inversion state.
    Type: Application
    Filed: April 28, 2003
    Publication date: October 28, 2004
    Inventor: Koji Ebara
  • Patent number: 6589336
    Abstract: Performing the post-implantation annealing for recovering crystallinity in a hydrogen atmosphere can successfully suppress the surface roughening on the ion-implanted layers without pre-implantation oxidation. This allows omission of the pre-implantation oxidation and allows ion implantation using only a photoresist film as a mask in a method for producing an epitaxial wafer having buried ion-implanted layers. Since an intentional formation of an oxide film, including such pre-implantation oxidation, on an epitaxial layer is omitted, the number of repetition of the thermal history exerted to the buried ion-implanted layers can be reduced, which effectively suppresses lateral diffusion of implanted ions. Since the formation and removal of the oxide film is thus no more necessary, the number of process steps in the production of the epitaxial wafer can dramatically be reduced.
    Type: Grant
    Filed: July 10, 2001
    Date of Patent: July 8, 2003
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Koji Ebara, Hiroki Ose, Yasuo Kasahara