Abstract: A display device includes a frame frequency conversion circuit configured to convert a frame frequency of an input display data and a timing control circuit configured to control a first drive circuit and a second drive circuit based on a frame frequency after the conversion. The display device generates at least two display areas on the display panel. The at least two display areas display images at different frame frequencies. The display device further includes a switch unit configured to display an image at the frame frequency before the conversion at one of the at least two display areas and configured to display an image at the frame frequency after the conversion at another one of the at least two display areas. At least one of a boundary position and a size of the at least two display areas varies with time.

Abstract: The present invention provides a technique for changing the number of taps in filter processing without the need for execution of branch processing. A filter processing device comprises: an arithmetic circuit that performs arithmetic processing for filtering operation; an internal register that retains data to be subjected to arithmetic processing in the arithmetic circuit and that receives the result of arithmetic processing from the arithmetic circuit as data to be written back thereto; and a data generator that generates data to be fed to the arithmetic circuit through use of the data retained in the internal register. Further, in the filter processing device, there is disposed a tap number control circuit that is capable of controlling the number of taps in filter processing according to a tap control signal applied thereto. In this configuration, no branch processing is required for controlling the number of taps by the use of the tap number control circuit.

Abstract: A resistive element is connected in series to a cathode terminal of an LED light source at a last stage (or an anode terminal of an LED light source at a first stage) of an LED chain, and a resistance value of the resistive element is configured to be variable in resistance value in accordance with a variation of voltage drops of the LEDs connected in series so that a resistance value of a resistive element connected to an LED chain having a large voltage drop has a smaller resistance value then a resistance value of a resistive element connected to an LED chain having a small voltage drop. With this configuration, the power, which has been wasted otherwise as heat in the backlight driver IC, may be dispersed to the resistive elements.

Abstract: Provided is a display device capable of producing an image of excellent quality with reduced flicker and little reduction in luminance, the display device including: a backlight having light sources such as LED devices arranged two-dimensionally, each of which may be individually modulated in luminance; a moving velocity detection unit VD1 (109) for detecting a moving velocity of an object in a video (for example, moving velocity of a foreground); and a luminance variation control unit (113) for automatically controlling luminance variations of the LED devices for each frame, in accordance with the moving velocity.

Abstract: The backlight device includes: a backlight including a plurality of light sources; and a backlight control part. The backlight includes a plurality of divided areas, and light sources disposed in each of the plurality of divided areas are chain-connected. The backlight control part includes at least one backlight control unit for controlling turning on and off of the backlight which includes the plurality of divided areas, with respect to the each divided area. The backlight control unit includes a selection unit for selecting one of divided areas, at least one backlight drive path. The selection unit selects the one of divided areas in a time division manner, and the light sources of the one of divided areas are driven by sharing the at least one backlight drive path in common.

Abstract: The present invention provides a functional block that executes video coding and video decoding based on H. 264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.

Abstract: The present invention provides a functional block that executes video coding and video decoding based on H.264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.

Abstract: A highly flexible semiconductor device of a stacked-type semiconductor device which transfers information by inductive coupling between inductors, in which LSI chips can be stacked even when a transmitter circuit and a receiver circuit are arranged at different positions from each other when viewed in a stacking direction. The semiconductor device has an interposer including a first inductor which is inductively coupled with a transmitter circuit of a first LSI chip to be stacked, and a second inductor which is inductively coupled with a receiver circuit of a second LSI chip to be stacked, the first inductor and the second inductor being electrically connected. An interchip communication is made from the first LSI chip to the second LSI chip.

Abstract: The present invention provides a technique for changing the number of taps in filter processing without the need for execution of branch processing. A filter processing device comprises: an arithmetic circuit that performs arithmetic processing for filtering operation; an internal register that retains data to be subjected to arithmetic processing in the arithmetic circuit and that receives the result of arithmetic processing from the arithmetic circuit as data to be written back thereto; and a data generator that generates data to be fed to the arithmetic circuit through use of the data retained in the internal register. Further, in the filter processing device, there is disposed a tap number control circuit that is capable of controlling the number of taps in filter processing according to a tap control signal applied thereto. In this configuration, no branch processing is required for controlling the number of taps by the use of the tap number control circuit.

Abstract: An external bus interface method including: receiving, via an access control unit, an access request conveyed through an external bus, and judging, via an access judging unit connected to the access control unit, whether the access request is to be honored or rejected, wherein upon receiving the access request, the access control unit sends to the access judging unit an access judging check request signal asking whether the requested address falls within one of access-permitted areas registered in the access judging unit, the access judging unit checks whether the requested address falls within one of the access-permitted areas registered in it and returns to the access control unit, an access judging check result signal indicating whether the access request is to be honored or rejected, and if the access judging check result signal indicates that the access request is to be rejected, the access control unit nullifies the access request.

Abstract: A display device includes a frame frequency conversion circuit configured to convert a frame frequency of an input display data and a timing control circuit configured to control a first drive circuit and a second drive circuit based on a frame frequency after the conversion. The display device generates at least two display areas on the display panel. The at least two display areas display images at different frame frequencies. The display device further includes a switch unit configured to display an image at the frame frequency before the conversion at one of the at least two display areas and configured to display an image at the frame frequency after the conversion at another one of the at least two display areas. At least one of a boundary position and a size of the at least two display areas varies with time.

Abstract: A resistive element (115) is connected in series to a cathode terminal of an LED light source at a last stage (or an anode terminal of an LED light source at a first stage) of an LED chain (116), and the resistive element (115) is configured to be variable in resistance value in accordance with a variation of voltage drops of the LEDs connected in series so that a resistive element connected to an LED chain having a large voltage drop has a small resistance value while a resistive element connected to an LED chain having a small voltage drop has a large resistance value. With this configuration, the power, which has been wasted otherwise as heat in the backlight driver IC, may be dispersed to the resistive elements.

Abstract: Provided is a display device capable of producing an image of excellent quality with reduced flicker and little reduction in luminance, the display device including: a backlight having light sources such as LED devices arranged two-dimensionally, each of which may be individually modulated in luminance; a moving velocity detection unit VD1 (109) for detecting a moving velocity of an object in a video (for example, moving velocity of a foreground); and a luminance variation control unit (113) for automatically controlling luminance variations of the LED devices for each frame, in accordance with the moving velocity.

Abstract: An external bus interface method including: receiving, via an access control unit, an access request conveyed through an external bus, and judging, via an access judging unit connected to the access control unit, whether the access request is to be honored or rejected, wherein upon receiving the access request, the access control unit sends to the access judging unit an access judging check request signal asking whether the requested address falls within one of access-permitted areas registered in the access judging unit, the access judging unit checks whether the requested address falls within one of the access-permitted areas registered in it and returns to the access control unit, an access judging check result signal indicating whether the access request is to be honored or rejected, and if the access judging check result signal indicates that the access request is to be rejected, the access control unit nullifies the access request.

Abstract: The backlight device includes: a backlight including a plurality of light sources; and a backlight control part. The backlight includes a plurality of divided areas, and light sources disposed in each of the plurality of divided areas are chain-connected. The backlight control part includes at least one backlight control unit for controlling turning on and off of the backlight which includes the plurality of divided areas, with respect to the each divided area. The backlight control unit includes a selection unit for selecting one of divided areas, at least one backlight drive path. The selection unit selects the one of divided areas in a time division manner, and the light sources of the one of divided areas are driven by sharing the at least one backlight drive path in common.

Abstract: A highly flexible semiconductor device of a stacked-type semiconductor device which transfers information by inductive coupling between inductors, in which LSI chips can be stacked even when a transmitter circuit and a receiver circuit are arranged at different positions from each other when viewed in a stacking direction. The semiconductor device has an interposer including a first inductor which is inductively coupled with a transmitter circuit of a first LSI chip to be stacked, and a second inductor which is inductively coupled with a receiver circuit of a second LSI chip to be stacked, the first inductor and the second inductor being electrically connected. An interchip communication is made from the first LSI chip to the second LSI chip.

Abstract: Access control unit sends to the access judging unit an access judging check request signal asking whether the requested address falls within one of the access-permitted areas registered in the access judging unit, the access judging unit checks whether the requested address falls within one of the access-permitted areas registered in it and returns to the access control unit an access judging check result signal indicating whether the access request is to be honored or rejected, and the access control unit permits access to the internal bus if the access judging check result signal indicates that the access request is to be honored, or rejects the access request otherwise.

Abstract: Access control unit sends to the access judging unit an access judging check request signal asking whether the requested address falls within one of the access-permitted areas registered in the access judging unit, the access judging unit checks whether the requested address falls within one of the access-permitted areas registered in it and returns to the access control unit an access judging check result signal indicating whether the access request is to be honored or rejected, and the access control unit permits access to the internal bus if the access judging check result signal indicates that the access request is to be honored, or rejects the access request otherwise.

Abstract: A processor capable of performing a filter processing in a high speed is provided. A computing unit comprises a computer for performing a filter processing. Data supply to the computer is performed by an internal register configured by a flip-flop. Data read from the internal register is outputted to a shift register and the data is supplied to the computer per cycle. And, the computing unit comprises a mechanism for changing a filter computing direction according to a motion vector, thereby preventing performance lowering due to branched command by performing a horizontal filtering and a vertical filtering by a same command.

Abstract: When an error is detected in an error detecting unit in a processor system, the error detecting unit outputs an error signal to an interrupt control unit, and the interrupt control unit outputs a value of an error address register and a control signal to a program counter control unit and rewrites a value of a program counter to a value of an error address register. By this means, the branching process by an error interrupt is realized. In this case, when the error is detected, the process of saving the value of the program counter at the time of error occurrence is not performed, and a specific save register and a control circuit for the recovery to the address at the time of the error occurrence after the end of the error processing are not provided.