Patents by Inventor Koji Hosoki

Koji Hosoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Processor
    Publication number: 20060053271
    Abstract: An object of the present invention is to provide a processor that can execute many computations with a small number of instruction codes. As far as multimedia processing is concerned, a plurality of computations of a same type are often executed concurrently and hence a plurality of computing units having a same function are used and mode information for controlling the plurality of units by an instruction unit for one computing unit is prepared in each instruction to execute a plurality of computations with a single instruction.
    Type: Application
    Filed: September 1, 2005
    Publication date: March 9, 2006
    Inventors: Kiyokazu Nishioka, Kazuhiko Tanaka, Yoshifumi Fujikawa, Toru Nojiri, Keiji Kojima, Koichi Terada, Yoshiki Kurokawa, Koji Hosoki
  • Processor including a plurality of computing devices
    Patent number: 6965981
    Abstract: As far as multimedia processing is concerned, a plurality of computations of a same type are often executed concurrently and hence a plurality of computing units having a same function are used and mode information for controlling the plurality of units by an instruction unit for one computing unit is prepared in each instruction to execute a plurality of computations with a single instruction.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: November 15, 2005
    Assignee: Renesas Technology Corporation
    Inventors: Kiyokazu Nishioka, Kazuhiko Tanaka, Yoshifumi Fujikawa, Toru Nojiri, Keiji Kojima, Koichi Terada, Yoshiki Kurokawa, Koji Hosoki
  • Processor
    Publication number: 20020099924
    Abstract: An object of the prevent invention is to provide a processor that can execute many computations with a small number of instruction codes.
    Type: Application
    Filed: January 24, 2002
    Publication date: July 25, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Kiyokazu Nishioka, Kazuhiko Tanaka, Yoshifumi Fujikawa, Toru Nojiri, Keiji Kojima, Koichi Terada, Yoshiki Kurokawa, Koji Hosoki
  • Parallel computing units having special registers storing large bit widths
    Patent number: 6401190
    Abstract: An object of the prevent invention is to provide a processor that can execute many computations with a small number of instruction codes. As far as multimedia processing is concerned, a plurality of computations of a same type are often executed concurrently and hence a plurality of computing units having a same function are used and mode information for controlling the plurality of units by an instruction unit for one computing unit is prepared in each instruction to execute a plurality of computations with a single instruction.
    Type: Grant
    Filed: September 12, 1997
    Date of Patent: June 4, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Kiyokazu Nishioka, Kazuhiko Tanaka, Yoshifumi Fujikawa, Toru Nojiri, Keiji Kojima, Koichi Terada, Yoshiki Kurokawa, Koji Hosoki