Patents by Inventor Koji Hosono
Koji Hosono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9870831Abstract: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.Type: GrantFiled: November 29, 2016Date of Patent: January 16, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroshi Nakamura, Kenichi Imamiya, Toshio Yamamura, Koji Hosono, Koichi Kawai
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Patent number: 9805797Abstract: According to one embodiment, a semiconductor memory device includes memory units each includes a first transistor, memory cell transistors, and a second transistor serially coupled between first and second ends. A memory cell transistor of each memory unit has its gate electrode coupled to each other. A bit line is coupled to the first ends. First and second drivers output voltage applied to selected and unselected first transistors, respectively. Third and fourth drivers output voltage applied to selected and unselected second transistors, respectively. A selector couples the gate electrode of the first transistor of each memory unit to the first or second driver, and that of the second transistor of each memory unit to the third or fourth driver.Type: GrantFiled: August 8, 2016Date of Patent: October 31, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventor: Koji Hosono
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Patent number: 9750168Abstract: A depth of a cavity formed in a storing member is set to a depth which allows a portion of an electronic component to project from the cavity in a state where the electronic component is stored in the cavity. A storing member includes guide portions each of which is a space communicating with the cavity and configured to guide the electronic component into the cavity. A guide portion is formed such that a guide opening portion which is an opening portion of the guide portion is larger than an opening portion of the cavity and the opening portion of the cavity falls within a region of the guide opening portion as viewed in a depth direction of the cavity. A space formed of the cavity and the guide portion is configured to store an entire electronic component in the inside thereof.Type: GrantFiled: August 23, 2016Date of Patent: August 29, 2017Assignee: Murata Manufacturing Co., Ltd.Inventors: Koji Hosono, Masatoshi Harada
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Publication number: 20170178739Abstract: A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.Type: ApplicationFiled: August 10, 2016Publication date: June 22, 2017Inventors: Hiroshi MAEJIMA, Koji HOSONO, Tadashi YASUFUKU, Noboru SHIBATA
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Patent number: 9659663Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line coupled to the first memory cell; and a second word line coupled to the second memory cell. When data is read from the first memory cell, a first voltage and a second voltage is applied to the first word line. A voltage of the second word line changes a first number of times while the first voltage is applied to the first word line, and the voltage changes a second number of times different from the first number of times while the second voltage is applied to the first word line.Type: GrantFiled: March 12, 2015Date of Patent: May 23, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masanobu Shirakawa, Takuya Futatsuyama, Koji Hosono
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Patent number: 9613713Abstract: According to one embodiment, a semiconductor memory device includes: first and second memory cells; first and second word lines coupled to the first and second memory cells, respectively. When data is read from the first memory cell, first and second voltages are applied to the first word line. A voltage of the second word line varies continuously by a first potential difference with time while the first voltage is applied to the first word line, and the voltage of the first word line varies continuously by a second potential difference with time while the second voltage is applied to the first word line.Type: GrantFiled: June 28, 2016Date of Patent: April 4, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masanobu Shirakawa, Takuya Futatsuyama, Koji Hosono
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Publication number: 20170076817Abstract: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.Type: ApplicationFiled: November 29, 2016Publication date: March 16, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi NAKAMURA, Kenichi Imamiya, Toshio Yamamura, Koji Hosono, Koichi Kawai
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Publication number: 20170064885Abstract: A depth of a cavity formed in a storing member is set to a depth which allows a portion of an electronic component to project from the cavity in a state where the electronic component is stored in the cavity. A storing member includes guide portions each of which is a space communicating with the cavity and configured to guide the electronic component into the cavity. A guide portion is formed such that a guide opening portion which is an opening portion of the guide portion is larger than an opening portion of the cavity and the opening portion of the cavity falls within a region of the guide opening portion as viewed in a depth direction of the cavity. A space formed of the cavity and the guide portion is configured to store an entire electronic component in the inside thereof.Type: ApplicationFiled: August 23, 2016Publication date: March 2, 2017Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Koji HOSONO, Masatoshi HARADA
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Publication number: 20170040065Abstract: A nonvolatile semiconductor memory device includes a memory cell array having first and second groups of memory strings, each memory string including first and second memory cells connected between select transistors. The nonvolatile semiconductor memory device further includes a first word line connected to the first memory cells of the memory strings, a second word line connected to the second memory cells of the memory strings, and a control unit configured to control application of control voltages to the select transistors and the word lines, such that a select line voltage is applied to the first word line and a non-select line voltage is applied to the second word line and not discharged while select transistors of the first group of memory strings are turned off and select transistors of the second group of memory strings are turned on.Type: ApplicationFiled: October 24, 2016Publication date: February 9, 2017Inventor: Koji HOSONO
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Patent number: 9536615Abstract: A nonvolatile semiconductor memory device includes a memory cell array having first and second groups of memory strings, each memory string including first and second memory cells connected between select transistors. The nonvolatile semiconductor memory device further includes a first word line connected to the first memory cells of the memory strings, a second word line connected to the second memory cells of the memory strings, and a control unit configured to control application of control voltages to the select transistors and the word lines, such that a select line voltage is applied to the first word line and a non-select line voltage is applied to the second word line and not discharged while select transistors of the first group of memory strings are turned off and select transistors of the second group of memory strings are turned on.Type: GrantFiled: September 9, 2015Date of Patent: January 3, 2017Assignee: Kabushiki Kaisha ToshibaInventor: Koji Hosono
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Patent number: 9536610Abstract: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.Type: GrantFiled: April 22, 2014Date of Patent: January 3, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Nakamura, Kenichi Imamiya, Toshio Yamamura, Koji Hosono, Koichi Kawai
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Publication number: 20160351262Abstract: According to one embodiment, a semiconductor memory device includes memory units each includes a first transistor, memory cell transistors, and a second transistor serially coupled between first and second ends. A memory cell transistor of each memory unit has its gate electrode coupled to each other. A bit line is coupled to the first ends. First and second drivers output voltage applied to selected and unselected first transistors, respectively. Third and fourth drivers output voltage applied to selected and unselected second transistors, respectively. A selector couples the gate electrode of the first transistor of each memory unit to the first or second driver, and that of the second transistor of each memory unit to the third or fourth driver.Type: ApplicationFiled: August 8, 2016Publication date: December 1, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Koji HOSONO
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Publication number: 20160307638Abstract: According to one embodiment, a semiconductor memory device includes: first and second memory cells; first and second word lines coupled to the first and second memory cells, respectively. When data is read from the first memory cell, first and second voltages are applied to the first word line. A voltage of the second word line varies continuously by a first potential difference with time while the first voltage is applied to the first word line, and the voltage of the first word line varies continuously by a second potential difference with time while the second voltage is applied to the first word line.Type: ApplicationFiled: June 28, 2016Publication date: October 20, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Koji HOSONO
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Patent number: 9460794Abstract: In a writing operation, a control circuit raises the voltage of a writing-prohibited bit line among a plurality of bit lines to a first voltage, and thereafter brings the writing-prohibited bit line into a floating state. Then, the control circuit raises the voltage of a writing bit line other than the writing-prohibited bit line to a second voltage. In this way, the control circuit prohibits writing into a memory transistor corresponding to the writing-prohibited bit line. On the other hand, the control circuit executes writing into a memory transistor corresponding to the writing bit line.Type: GrantFiled: October 6, 2014Date of Patent: October 4, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Maejima, Koji Hosono
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Patent number: 9449689Abstract: A semiconductor memory device includes a string of memory cell transistors that are connected to each other in series. A selection transistor is connected between one end of the string of the memory cell transistors and one of a source line and a bit line. A line is selectively connected to a gate electrode of the selection transistor, a driver, or a node that supplies an unselected voltage, or is set to be in a floating state.Type: GrantFiled: January 26, 2015Date of Patent: September 20, 2016Assignee: Kabushiki Kaisha ToshibaInventor: Koji Hosono
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Patent number: 9449691Abstract: A memory device includes a plurality of memory blocks, and a row decoder including a plurality of decoders including a first decoder and a second decoder, the first decoder being configured to output a first block selection signal for selecting one of the memory blocks and a control signal for causing the second decoder to output a second block selection signal for selecting another one of the memory blocks.Type: GrantFiled: September 16, 2015Date of Patent: September 20, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Koji Hosono, Tomonori Kurosawa
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Patent number: 9443593Abstract: According to one embodiment, a semiconductor memory device includes memory units each includes a first transistor, memory cell transistors, and a second transistor serially coupled between first and second ends. A memory cell transistor of each memory unit has its gate electrode coupled to each other. A bit line is coupled to the first ends. First and second drivers output voltage applied to selected and unselected first transistors, respectively. Third and fourth drivers output voltage applied to selected and unselected second transistors, respectively. A selector couples the gate electrode of the first transistor of each memory unit to the first or second driver, and that of the second transistor of each memory unit to the third or fourth driver.Type: GrantFiled: February 19, 2015Date of Patent: September 13, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Koji Hosono
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Publication number: 20160240264Abstract: A semiconductor memory device includes a first memory cell, a first word line electrically connected to a gate of the first memory cell, a first bit line electrically connected to one end of the first memory cell, and a controller configured to execute a write operation, which includes a first cycle and a second cycle that is executed after the first cycle. The first cycle includes a first operation of applying a program voltage to the first word line, a second operation executed after the first operation of applying a first voltage to the first bit line and a second voltage lower than the first voltage to the first word line, and a third operation executed after the second operation of applying a verify voltage to the first word line. The second cycle includes the first operation and then the third operation, and excludes the second operation.Type: ApplicationFiled: February 17, 2016Publication date: August 18, 2016Inventor: Koji HOSONO
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Patent number: 9368210Abstract: According to one embodiment, a semiconductor memory device includes a memory cells, a selection transistor, a memory string, a block, and a transfer circuit. The memory cells are stacked on a semiconductor substrate. In the memory string, the memory cells and the selection transistor are connected in series. The block includes a plurality of memory strings. In data write and read, the transfer circuit transfers a positive voltage to a select gate line associated with a selected memory string in a selected block, and a negative voltage to a select gate line associated with an unselected memory string in the selected block, and to a select gate line associated with an unselected block.Type: GrantFiled: June 17, 2015Date of Patent: June 14, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Maejima, Koji Hosono
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Patent number: RE46526Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.Type: GrantFiled: October 22, 2014Date of Patent: August 29, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Dai Nakamura, Hiroyuki Kutsukake, Kenji Gomikawa, Takeshi Shimane, Mitsuhiro Noguchi, Koji Hosono, Masaru Koyanagi, Takashi Aoi