Patents by Inventor Koji IKEBATA

Koji IKEBATA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE HAVING BIT LINE HIERARCHICALLY STRUCTURED
    Publication number: 20130294137
    Abstract: Disclosed herein is a semiconductor device that includes a plurality of memory cells; a local bit line coupled to the memory cells; a global bit line; and a first switch circuit coupled between the global bit line and the local bit line, the first switch circuit electrically connecting the local bit line to the global bit line when at least one of first and second control signals is in an active state, and the first switch circuit electrically disconnecting the local bit line to the global bit line when both of the first and second control signals are in an inactive state.
    Type: Application
    Filed: May 7, 2013
    Publication date: November 7, 2013
    Applicant: Elpida Memory, Inc.
    Inventors: Noriaki MOCHIDA, Hiroyuki UNO, Koji IKEBATA, Kyoichi NAGATA