Abstract: A data transmitting apparatus and a data receiving apparatus, which are capable of retransmitting a packet even when a retransmission request is made by a client after transmitting a session close notice packet to the client. A session is closed by a session closing means 105 when a predetermined period of time has passed after transmitting the session close notice packet, which is generated by a control command generating means 102 as the session close notice packet, from a packet transmitting means 103 to the client.

Abstract: The transmission end (header compression end) and the reception end (header decompression end) share the same timestamp calculation information which is previously prepared. At the transmission end, in the case that the timestamp of the current packet to be subjected to header compression cannot be compressed with the current timestamp calculation information S33, the history record which covers timestamp calculation information so far transmitted is referred to determine S35 which to transmit a packet header carrying the timestamp without updating the current timestamp calculation information S37, or a packet header carrying the timestamp S34 by updating the current timestamp calculation information.

Abstract: A packet compressor 12 operates under a reliable mode or an optimistic mode. A mode determination unit 31 counts the number of ACK packets or NACK packets received by a unit time X by an ACK/NACK packet receiver 14. When the counted number of NACK packets is larger than a predetermined value Y, the mode determination unit 31 switches the operation mode of the packet compressor 12 to the reliable mode. When the counted number of ACK packets is larger than a predetermined value Z, the mode determination unit 31 switches the operation mode of the packet compressor 12 to the optimistic mode.

Abstract: In a header decompression apparatus 709, a header decompressor 703 refers to reference information stored in a reference information manager 707 to decompress a compressed header of a packet received by a packet receiver 704. An error detector 702 detects a CRC error in the packet with its header decompressed by the packet receiver 704, and outputs only a correct packet. A successive error counter 705 counts the number of successive errors detected by the error detector 702. A successive decompression success counter 706 counts the number of decompression successes that successively appear. By referring to these counted numbers, an update request unit 708 transmits an update request to a transmitting side as required. A reference information manager 707 manages the reference information for header decompression. With this structure, the header decompression apparatus can request update of the reference information based on the state of the error.

Abstract: A data transmitter 10 transmits packets each with a sequence number and a priority added. A data receiver 20 detects any packet loss by referring to the sequence numbers added to the packets, and if detecting any packet of high priority as having been lost, requests for packet retransmission. Based on information about thus detected packet loss, the data receiver 20 generates and transmits an RR packet 110 indicating the packet reception state. The data transmitter 10 extracts from the RR packet 110 a packet loss ratio 200, and therewith, changes manners of priority assignment. The manners are so changed that the packet of high priority is found with a lower ratio when the packet loss ratio 200 is high, and when the packet loss ratio 200 is low, found with a higher ratio.

Abstract: The present invention provides a variable-length encoding and decoding apparatus which, when an overlap of a variable-length code and a synchronizing word is generated on a bit stream due to a transmission error or the like in the variable-length encoding and decoding apparatus of an image compression bit stream, can exactly detect the synchronizing word and a state where the overlap is generated.

Abstract: In a transmitter, a motion detector detects a motion amount of a coded block. A buffer memorizes a detected motion amount. A buffer controller controls the buffer to read the motion amounts in the order opposed to the writing order. A switch selects one of outputs. In a receiver, a sync word detector discriminates first and second sync words. A primary frame memory memorizes an actually decoded image. A secondary frame memory memorizes a predicted image corresponding to the actually decoded image. Memory controllers read out the image information of coding blocks from the corresponding frame memories in an order opposed to the writing order. A switch selects either one of the information of the primary or secondary frame memories.

Abstract: The invention provides a decoding method of coded moving image signal and a decoding apparatus using the same, being a decoding method of moving image signal obtained by coding input digital moving image signals, gathering in a unit of one picture, issuing bit streams including the time information of present picture, accumulating the bit streams in the transmission side buffer, and decoding the bit streams being controlled to code a next picture when the buffer residue capacity becomes smaller than a certain threshold, characterized by calculating the time between pictures from the generated coding amount of the received previous picture, the threshold and transmission speed, comparing the time information extracted from the input bit stream and the time between pictures, and judging whether the extracted time information is correct or not.

Abstract: This is provided a dual-surface mounting type semiconductor integrated circuit device capable of achieving reductions in chip area and consumption power. In the dual-surface mounting type semiconductor integrated circuit device, a specified circuit for implementing a function common to integrated circuit chips and mounted on both surfaces of a chip mounting section of a lead frame is provided only for the integrated circuit chip of one surface, and an output signal of the specified circuit provided only for the integrated circuit chip of this one surface is transmitted to the integrated circuit chip of the other surface via bonding wires and an internal lead.

Abstract: Important quantized coefficients having absolute values which are higher than a threshold value are extracted from each of quantized coefficient streams into which a digital image signal is transformed, and an important quantized coefficient stream composed of the important quantized coefficients and zero-valued quantized coefficients is produced on condition that the number of important quantized coefficients and zero-valued quantized coefficients is equal to that of quantized coefficients in each quantized coefficient stream and positions of the important quantized coefficients in the important quantized coefficient stream are the same as those in a corresponding quantized coefficient stream. Also, a lesser-important quantized coefficient stream is produced by subtracting the important quantized coefficient stream from the corresponding quantized coefficient stream.

Abstract: An input picture signal is divided into blocks. The blocks are grouped into groups each having a plurality of blocks. The input picture signal is encoded into a second picture signal block by block. The second picture signal uses a variable length code. An error correction signal is added to the second picture signal for each of the groups. A signal of a start address and a signal of a location address are added to the second picture signal for each of the groups. The start address represents a position of a bit within each of the groups. The location address representing a spatial position of a block within each of the groups.

Abstract: A semiconductor memory device according to the present invention includes: a memory cell array including (2.sup.n +m) memory cells, wherein n and m are integers satisfying the relationship 2.sup.n <2.sup.n +m<2.sup.n+1 ; an address decoder for receiving an address signal of (n+l) bits and for specifying one of the (2.sup.

Abstract: An integrated circuit which can be operated in a test mode includes a test input terminal for instructing the switching between an actual use mode and a test mode, a plurality of input terminals, an AND gate for performing logic operations on the input signals from the input terminals, a plurality of flip-flops for storing each of the input signals from the remaining plurality of input terminals by using the outpout of the AND gate as a timing signal, a decoder for producing a test mode designating signal to select one test mode from a plurality of test modes in response to each of the outputs of the flip-flops, and a control circuit for operating a processing circuit in the test mode designated by the test mode designating signal in response to the test mode setting signal from the test input and the test mode designating signal from the decoder.