Patents by Inventor Koji IWABU

Koji IWABU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and semiconductor device manufacturing method
    Patent number: 10854560
    Abstract: A semiconductor device includes: an island that is formed by a metallic layer including a single metallic layer or a plurality of different metallic layers; a semiconductor chip provided upon an upper surface of the island, and having a pair of side portions mutually opposing each other; a plurality of signal terminals disposed at an external periphery of at least the pair of side portions of the semiconductor chip, and formed by the metallic layer; a grounding terminal disposed at an external periphery of the plurality of signal terminals, and formed by the metallic layer; electrically conductive connection members that are connected between each of a plurality of electrodes of the semiconductor chip and each of the plurality of signal terminals; sealing resin that seals the island, the semiconductor chip, the electrically conductive connection members, the plurality of signal terminals, and the grounding terminal, so that a lower surface of the island, lower surfaces of the plurality of signal terminals, an
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: December 1, 2020
    Assignees: AOI Electronics Co., Ltd., Mitsubishi Electric Corporation
    Inventors: Shuichi Sawamoto, Koji Iwabu, Katsuhiro Takao, Akihito Hirai, Joichi Saito
  • Semiconductor device packaging with metallic shielding layer
    Patent number: 10854557
    Abstract: A semiconductor device includes: an island that is formed by a metallic layer including a single metallic layer or a plurality of different metallic layers; a semiconductor chip provided upon an upper surface of the island, and having a pair of side portions mutually opposing each other; a plurality of signal terminals disposed at an external periphery of at least the pair of side portions of the semiconductor chip, and formed by the metallic layer; a grounding terminal disposed at an external periphery of the plurality of signal terminals, and formed by the metallic layer; electrically conductive connection members that are connected between each of a plurality of electrodes of the semiconductor chip and each of the plurality of signal terminals; sealing resin that seals the island, the semiconductor chip, the electrically conductive connection members, the plurality of signal terminals, and the grounding terminal, so that a lower surface of the island, lower surfaces of the plurality of signal terminals, an
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: December 1, 2020
    Assignees: AOI Electronics Co., Ltd., Mitsubishi Electric Corporation
    Inventors: Shuichi Sawamoto, Koji Iwabu, Katsuhiro Takao, Akihito Hirai, Joichi Saito
  • Semiconductor Device and Semiconductor Device Manufacturing Method
    Publication number: 20190326227
    Abstract: A semiconductor device includes: an island that is formed by a metallic layer including a single metallic layer or a plurality of different metallic layers; a semiconductor chip provided upon an upper surface of the island, and having a pair of side portions mutually opposing each other; a plurality of signal terminals disposed at an external periphery of at least the pair of side portions of the semiconductor chip, and formed by the metallic layer; a grounding terminal disposed at an external periphery of the plurality of signal terminals, and formed by the metallic layer; electrically conductive connection members that are connected between each of a plurality of electrodes of the semiconductor chip and each of the plurality of signal terminals; sealing resin that seals the island, the semiconductor chip, the electrically conductive connection members, the plurality of signal terminals, and the grounding terminal, so that a lower surface of the island, lower surfaces of the plurality of signal terminals, an
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: Shuichi SAWAMOTO, Koji IWABU, Katsuhiro TAKAO, Akihito HIRAI, Joichi SAITO
  • Semiconductor Device and Semiconductor Device Manufacturing Method
    Publication number: 20180197822
    Abstract: A semiconductor device includes: an island that is formed by a metallic layer including a single metallic layer or a plurality of different metallic layers; a semiconductor chip provided upon an upper surface of the island, and having a pair of side portions mutually opposing each other; a plurality of signal terminals disposed at an external periphery of at least the pair of side portions of the semiconductor chip, and formed by the metallic layer; a grounding terminal disposed at an external periphery of the plurality of signal terminals, and formed by the metallic layer; electrically conductive connection members that are connected between each of a plurality of electrodes of the semiconductor chip and each of the plurality of signal terminals; sealing resin that seals the island, the semiconductor chip, the electrically conductive connection members, the plurality of signal terminals, and the grounding terminal, so that a lower surface of the island, lower surfaces of the plurality of signal terminals, an
    Type: Application
    Filed: May 19, 2016
    Publication date: July 12, 2018
    Inventors: Shuichi SAWAMOTO, Koji IWABU, Katsuhiro TAKAO, Akihito HIRAI, Joichi SAITO