Abstract: It is possible to control a welding in a high speed and a high precision large electric current, and consumption electric power is also reduced. In the welding transformer, a loop magnetic core 25, a wound primary coil 12, plural positive side coils 14 and plural negative side coils 16 that are alternately sandwiched between respective gaps 12a of the primary coil 12, are comprised. A coil is fixed on the other surface of a contact base member 62. On the other surface of the contact base member 62, a first connection polar board 44 is electrically connected to a positive side electric conductor 30 through the first connection polar board 44. A negative side coil 16 is electrically connected to a negative side electric conductor 32. The connecting part of the positive side coil 14 and the negative side coil 16 is electrically connected to the third connection polar board 48.

Abstract: It is possible to control a welding in a high speed and a high precision large electric current, and consumption electric power is also reduced. In the welding transformer, a loop magnetic core 25, a wound primary coil 12, plural positive side coils 14 and plural negative side coils 16 that are alternately sandwiched between respective gaps 12a of the primary coil 12, are comprised. A coil is fixed on the other surface of a contact base member 62. On the other surface of the contact base member 62, a first connection polar board 44 is electrically connected to a positive side electric conductor 30 through the first connection polar board 44. A negative side coil 16 is electrically connected to a negative side electric conductor 32. The connecting part of the positive side coil 14 and the negative side coil 16 is electrically connected to the third connection polar board 48.

Abstract: An integrated circuit including a shared memory connected to a bus, an audio/multiplex/de-multiplex processor accessing the shared memory via the bus, a video processor performing heavy processes accessing the shared memory via the bus, and a local memory accessed by the video processor without passing through the bus. The integrated circuit avoids a latency time caused by access contention, such that a probability that the integrated circuit can complete processes to be done in real time is increased. Image data is displayed on the display device smoothly without deterioration of quality of display.

Abstract: The moving picture image pickup device includes an image pickup section for obtaining a picked-up moving picture, and an image processing section for processing, per frame, the picked-up moving picture and creating a storage moving picture. The image processing section designates, upon a user's instruction, object images in the picked-up moving picture; sets object trimming images for clipping, out of the picked-up moving picture, the object images, respectively; follows the object images and moving, per frame, the object trimming images in accordance with the object images; sets, per frame, the object trimming images as a first trimming image; sets one image enclosing the object trimming images as a second trimming image; calculates and compares the data sizes of the first and the second trimming images; and selects, as the storage moving picture, an image having a smaller data size, from the first trimming image or the second trimming image.

Abstract: The moving picture image pickup device includes an image pickup section for obtaining a picked-up moving picture, and an image processing section for processing, per frame, the picked-up moving picture and creating a storage moving picture. The image processing section designates, upon a user's instruction, object images in the picked-up moving picture; sets object trimming images for clipping, out of the picked-up moving picture, the object images, respectively; follows the object images and moving, per frame, the object trimming images in accordance with the object images; sets, per frame, the object trimming images as a first trimming image; sets one image enclosing the object trimming images as a second trimming image; calculates and compares the data sizes of the first and the second trimming images; and selects, as the storage moving picture, an image having a smaller data size, from the first trimming image or the second trimming image.

Abstract: A bus arbitrating device (100) arbitrates the data transfer request for a plurality of bus-master (11)-(13) connected to a bus (10), and comprises a bus assignment deciding unit (20) and a measurement control unit (30). The measurement control unit (30) includes a time counter (31), a comparator (32), and a timer register (33). The comparator (32) compares a system operating time measured by the time counter (31), with a time period set in the timer register (33). When the system operating time exceeds the time period, the comparator (32) notifies the bus assignment deciding unit (20) of the fact. The bus assignment deciding unit (20) chooses one from a plurality of bus arbitration algorithms as a new bus arbitration algorithm, and arbitrates the bus. Consequently, the deviation of the right of bus use of each bus master can be avoided.

Abstract: In a data-sending device, a data generation section provides input data itself or a bit-inverted version of the input data as intermediate data and generates an inversion signal that indicates whether or not the intermediate data is the bit-inverted version of the input data. An encrypting section generates scrambled data by inserting the inversion signal in the intermediate data at a bit position. A data-receiving device removes the inversion signal from the scrambled data, and restores the input data based on the inversion signal.

Abstract: A total specification is divided into a hardware specification and a software specification. With respect to the hardware specification, a first hardware description is described. With respect to the software specification, an object program is generated, which is converted into a second hardware description. The first and second hardware descriptions are logically synthesized into a net list, which includes a part that fulfills the software specification. Since the object program is converted into the second hardware description, which is logically synthesized, the redundancy of the program can be removed and cost for manufacturing hardware can be reduced.

Abstract: A power management system for an integrated circuit has a signal line, a management data generating unit connected to the signal line, and a plurality of management data using units each connected to the signal line. The management data generating unit outputs, to the signal line, power management data for managing power consumption in each of the management data using units, the power management data corresponding to the state of the management data generating unit. Each of the management data using units reads the power management data for common use from the signal line and controls power consumed by the management data using unit based on the power management data.

Abstract: The integrated circuit comprises: a shared memory connected to a bus; an audio/multiplex/de-multiplex processor accessing the shared memory via the bus; a video processor performing heavy processes accessing the shared memory via the bus; and a local memory accessed by the video processor without passing through the bus. Avoiding latency time caused by access contention, probability that the integrated circuit can complete processes to be done in real time increases. Image data is displayed on the display device smoothly without deterioration of quality of display.

Abstract: In a data-sending device, a data generation section provides input data itself or a bit-inverted version of the input data as intermediate data and generates an inversion signal that indicates whether or not the intermediate data is the bit-inverted version of the input data. An encrypting section generates scrambled data by inserting the inversion signal in the intermediate data at a bit position. A data-receiving device removes the inversion signal from the scrambled data, and restores the input data based on the inversion signal.

Abstract: After a program is inputted in the high-level synthesis of system design, blocks each for implementing at least one function and an HW resource connection graph showing a plurality of HW resources and a wiring structure connecting the HW resources are generated. From a database storing the HW resources, data on the size of each of the HW resources is inputted such that the HW resources are provisionally placed and a contribution rate of each of parameters which affect power consumption and the like in each of wires between blocks with respect to all the wires is calculated as a weight of signal lines between blocks. Block generation is performed repeatedly till the weight of signal lines between blocks in each of the wires between blocks becomes a threshold value or less. If the weight of signal lines between blocks becomes the threshold value or less, an HDL is outputted.

Abstract: An object of the invention, in a semiconductor circuit or, more particularly, in an LSI on which a DRAM and a logic circuit are merged, is to decrease the frequency of times of refreshing operations to thereby achieve both reduction in power consumption and prevention of deterioration in the performance of the logic circuit caused by an increase in the memory access time due to contention between refresh and DRAM access of the logic circuit. To achieve the object, the refreshing is done only for rows storing the data used by the logic portion. Further, arbitrary data for which periods from being written in to being read out are overlapping or close to each other are allocated to the same row of the DRAM so as to be stored thereon, and the row is refreshed only during the period of time that the data stored thereon is live.

Abstract: A power management system for an integrated circuit has a signal line, a management data generating unit connected to the signal line, and a plurality of management data using units each connected to the signal line. The management data generating unit outputs, to the signal line, power management data for managing power consumption in each of the management data using units, the power management data corresponding to the state of the management data generating unit. Each of the management data using units reads the power management data for common use from the signal line and controls power consumed by the management data using unit based on the power management data.

Abstract: The present invention provides for setting the block-size suitably in each address space in order to deal with the difference of the scope within the spatial locality in the address space, and to suppress the generating of the unnecessary replacing.

Abstract: An object of the invention, in a semiconductor circuit or, more particularly, in an LSI on which a DRAM and a logic circuit are merged, is to decrease the frequency of times of refreshing operations to thereby achieve both reduction in power consumption and prevention of deterioration in the performance of the logic circuit caused by an increase in the memory access time due to contention between refresh and DRAM access of the logic circuit.

Abstract: In the transmitter which carries out burst transmission using information data as a packet, if the status is divided into four modes, namely, burst stop mode, burst rising mode, burst continuous mode, and burst falling mode, a waveform shaping equipment designed to read out shaped waveform data for each mode from outputs of either of the two memory tables, the first memory table which holds waveform data for specific data patterns used in common in burst rising mode and burst falling mode and the second memory table which holds waveform data for all data patterns used in the burst continuous mode, or a waveform shaping equipment comprising the third memory table which holds waveform data corresponding to all the data patterns used in the burst rising mode and the fourth memory table which holds waveform data corresponding to all data patterns used in the burst falling mode and generating shaped waveform data by synthesizing the two outputs of the third and the fourth memory tables at the time of burst continu

Abstract: In the transmitter which carries out burst transmission using information data as a packet, if the status is divided into four modes, namely, burst stop mode, burst rising mode, burst continuous mode, and burst falling mode, a waveform shaping equipment designed to read out shaped waveform data for each mode from outputs of either of the two memory tables, the first memory table which holds waveform data for specific data patterns used in common in burst rising mode and burst falling mode and the second memory table which holds waveform data for all data patterns used in the burst continuous mode, or a waveform shaping equipment comprising the third memory table which holds waveform data corresponding to all the data patterns used in the burst rising mode and the fourth memory table which holds waveform data corresponding to all data patterns used in the burst falling mode and generating shaped waveform data by synthesizing the two outputs of the third and the fourth memory tables at the time of burst continu

Abstract: In the transmitter which carries out burst transmission using information data as a packet, if the status is divided into four modes, namely, burst stop mode, burst rising mode, burst continuous mode, and burst falling mode, a waveform shaping equipment designed to read out shaped waveform data for each mode from outputs of either of the two memory tables, the first memory table which holds waveform data for specific data patterns used in common in burst rising mode and burst falling mode and the second memory table which holds waveform data for all data patterns used in the burst continuous mode, or a waveform shaping equipment comprising the third memory table which holds waveform data corresponding to all the data patterns used in the burst rising mode and the fourth memory table which holds waveform data corresponding to all data patterns used in the burst falling mode and generating shaped waveform data by synthesizing the two outputs of the third and the fourth memory tables at the time of burst continu