Abstract: A test circuit includes a plurality of circuit blocks having a same circuit construction and a same function, a plurality of internal test circuits each corresponding to a different one of the plurality of circuit blocks, an OR circuit which outputs a logical sum result of a test result output by each of the plurality of circuit blocks as a first result signal, an AND circuit which outputs a logical product result of the test result output by each of the plurality of circuit blocks as a second result signal, and a decision circuit which outputs a consistent comparison result between the first result signal and the second result signal as a final result signal.

Abstract: When a dynamic fault test is to be performed on a plurality of divisional circuits, in order to perform the dynamic fault test also on a circuit in which the divisional circuits are combined, and to increase a fault detection rate of dynamic fault, a scan test circuit for a semiconductor device including a plurality of divisional circuits obtained by dividing a logical circuit incorporated in the semiconductor device, includes: a clock control circuit; and a first scan path and a second scan path which are provided in each of at least two of the plurality of divisional circuits. The first scan path includes peripheral scan FFs corresponding to scan FFs which transmit and receive signals to and from another one of the plurality of divisional circuits, of scan FFs included in each of the divisional circuits. The second scan path includes internal scan FFs corresponding to scan FFs other than the peripheral scan FFs, of the scan FFs included in each of the plurality of divisional circuits.

Abstract: A scan-path flip-flop circuit for an integrated circuit memory comprises a number of successively arranged flip-flops. Each flip-flop comprises a master latching circuit for latching a first signal supplied from an associated input terminal of the integrated circuit memory in response to a normal-mode clock signal, supplying the latched first signal to the integrated circuit memory, and further latching a second signal in response to a first scan-mode clock signal. The first signal from the master latching circuit is latched in a slave latching circuit in response to the normal-mode clock signal, and the second signal from the master latching circuit is latched in the slave latching circuit in response to a second scan-mode clock signal. The slave latching circuit of each preceding flip-flop is connected to the master latching circuit of a succeeding flip-flop for shifting the second signal in response to the first scan-mode clock signal.

Abstract: A scan flip-flop (100A) that may operate as a positive flip-flop or a negative flip-flop in a normal operating mode has been disclosed. Scan flip-flop (100A) may include a master latching circuit (11), a slave latching circuit (12), and a clock circuit (13A). Clock circuit (13A) may receive a signal (XA), a control signal (control), and a mode signal (SCN). Signal (XA) may select between a positive flip-flop operation and a negative flip-flop operation when in a normal operating mode. Mode signal (SCN) may select between a normal operating mode and a scan test mode. Control signal (control) may disable signal (XA) so that scan flip-flop (100A) may operate in a known mode, such as a positive flip-flop, regardless as to the value of signal (XA). Scan flip-flop (100A) may reduce logic gates in clock lines which may be required in a conventional approach.

Abstract: A scan-path flip-flop circuit for an integrated circuit memory comprises a number of successively arranged flip-flops. Each flip-flop comprises a master latching circuit for latching a first signal supplied from an associated input terminal of the integrated circuit memory in response to a normal-mode clock signal, supplying the latched first signal to the integrated circuit memory, and further latching a second signal in response to a first scan-mode clock signal. The first signal from the master latching circuit is latched in a slave latching circuit in response to the normal-mode clock signal, and the second signal from the master latching circuit is latched in the slave latching circuit in response to a second scan-mode clock signal. The slave latching circuit of each preceding flip-flop is connected to the master latching circuit of a succeeding flip-flop for shifting the second signal in response to the first scan-mode clock signal.

Abstract: A scan flip-flop (100A) that may operate as a positive flip-flop or a negative flip-flop in a normal operating mode has been disclosed. Scan flip-flop (100A) may include a master latching circuit (11), a slave latching circuit (12), and a clock circuit (13A). Clock circuit (13A) may receive a signal (XA), a control signal (control), and a mode signal (SCN). Signal (XA) may select between a positive flip-flop operation and a negative flip-flop operation when in a normal operating mode. Mode signal (SCN) may select between a normal operating mode and a scan test mode. Control signal (control) may disable signal (XA) so that scan flip-flop (100A) may operate in a known mode, such as a positive flip-flop, regardless as to the value of signal (XA). Scan flip-flop (100A) may reduce logic gates in clock lines which may be required in a conventional approach.