Patents by Inventor Koji Kashimoto

Koji Kashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10594149
    Abstract: A battery management method and apparatus. In one embodiment of the method, a source current is divided into Ic and Icr. Ic is transmitted to and charges a battery. A first voltage is generated that is related to Icr. The first voltage is converted into a first digital signal. A processing unit receives and processes the first digital signal in accordance with instructions stored in a memory. The transmission of Ic to the battery is interrupted in response to the processing unit processing the first digital signal. Current provided by the battery is divided into Idc and Idcr. Idc is transmitted to a device. A second voltage is generated that is related to Idcr. The second voltage is converted into a second digital signal. The processing unit receives and processes the second digital signal in accordance with instructions stored in the memory. The transmission of Idc to the battery is interrupted in response to the processing unit processing the second digital signal.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: March 17, 2020
    Assignee: Renesas Electronics America Inc.
    Inventors: Tetsuo Sato, Tsutomu Kawano, Koji Kashimoto, Takao Hidaka, Tsuyoshi Ota, Ryoji Kato
  • Publication number: 20170264121
    Abstract: A battery management method and apparatus. In one embodiment of the method, a source current is divided into Ic and Icr. Ic is transmitted to and charges a battery. A first voltage is generated that is related to Icr. The first voltage is converted into a first digital signal. A processing unit receives and processes the first digital signal in accordance with instructions stored in a memory. The transmission of Ic to the battery is interrupted in response to the processing unit processing the first digital signal. Current provided by the battery is divided into Idc and Idcr. Idc is transmitted to a device. A second voltage is generated that is related to Idcr. The second voltage is converted into a second digital signal. The processing unit receives and processes the second digital signal in accordance with instructions stored in the memory. The transmission of Idc to the battery is interrupted in response to the processing unit processing the second digital signal.
    Type: Application
    Filed: May 26, 2017
    Publication date: September 14, 2017
    Inventors: Tetsuo Sato, Tsutomu Kawano, Koji Kashimoto, Takao Hidaka, Tsuyoshi Ota, Ryoji Kato
  • Patent number: 9667083
    Abstract: A battery management method and apparatus. In one embodiment of the method, a source current is divided into Ic and Icr. Ic is transmitted to and charges a battery. A first voltage is generated that is related to Icr. The first voltage is converted into a first digital signal. A processing unit receives and processes the first digital signal in accordance with instructions stored in a memory. The transmission of Ic to the battery is interrupted in response to the processing unit processing the first digital signal. Current provided by the battery is divided into Idc and Idcr. Idc is transmitted to a device. A second voltage is generated that is related to Idcr. The second voltage is converted into a second digital signal. The processing unit receives and processes the second digital signal in accordance with instructions stored in the memory. The transmission of Idc to the battery is interrupted in response to the processing unit processing the second digital signal.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: May 30, 2017
    Assignee: Renesas Electronics America Inc.
    Inventors: Tetsuo Sato, Tsutomu Kawano, Koji Kashimoto, Takao Hidaka, Tsuyoshi Ota, Ryoji Kato
  • Publication number: 20150077062
    Abstract: A battery management method and apparatus. In one embodiment of the method, a source current is divided into Ic and Icr. Ic is transmitted to and charges a battery. A first voltage is generated that is related to Icr. The first voltage is converted into a first digital signal. A processing unit receives and processes the first digital signal in accordance with instructions stored in a memory. The transmission of Ic to the battery is interrupted in response to the processing unit processing the first digital signal. Current provided by the battery is divided into Idc and Idcr. Idc is transmitted to a device. A second voltage is generated that is related to Idcr. The second voltage is converted into a second digital signal. The processing unit receives and processes the second digital signal in accordance with instructions stored in the memory. The transmission of Idc to the battery is interrupted in response to the processing unit processing the second digital signal.
    Type: Application
    Filed: November 25, 2014
    Publication date: March 19, 2015
    Inventors: Tetsuo Sato, Tsutomu Kawano, Koji Kashimoto, Takao Hidaka, Tsuyoshi Otal, Ryoji Kato
  • Patent number: 8901894
    Abstract: A battery management method and apparatus. In one embodiment of the method, a source current is divided into Ic and Icr. Ic is transmitted to and charges a battery. A first voltage is generated that is related to Icr. The first voltage is converted into a first digital signal. A processing unit receives and processes the first digital signal in accordance with instructions stored in a memory. The transmission of Ic to the battery is interrupted in response to the processing unit processing the first digital signal. Current provided by the battery is divided into Idc and Idcr. Idc is transmitted to a device. A second voltage is generated that is related to Idcr. The second voltage is converted into a second digital signal. The processing unit receives and processes the second digital signal in accordance with instructions stored in the memory. The transmission of Idc to the battery is interrupted in response to the processing unit processing the second digital signal.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: December 2, 2014
    Assignee: Renesas Electronics America Inc.
    Inventors: Tetsuo Sato, Tsutomu Kawano, Koji Kashimoto, Takao Hidaka, Tsuyoshi Ota, Ryoji Kato
  • Patent number: 8638067
    Abstract: In one embodiment of the cold end switch battery management control method, a battery generates an output voltage at a positive terminal thereof. A first control voltage is also generated by an integrated circuit. A gate of a field effect transistor (FET) receives the first control voltage, wherein the FET comprises a drain and a source with the source coupled to a negative terminal of the battery. The FET transmits current towards the battery in response to the gate receiving the first control voltage, wherein the first control voltage is greater than the output voltage, and wherein the first control voltage is less than a breakdown voltage of the integrated circuit.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: January 28, 2014
    Assignee: Renesas Electronics America Inc.
    Inventors: Tetsuo Sato, Tsutomu Kawano, Koji Kashimoto, Takao Hidaka, Tsuyoshi Ota, Ryoji Kato
  • Publication number: 20130063093
    Abstract: In one embodiment of the cold end switch battery management control method, a battery generates an output voltage at a positive terminal thereof. A first control voltage is also generated by an integrated circuit. A gate of a field effect transistor (FET) receives the first control voltage, wherein the FET comprises a drain and a source with the source coupled to a negative terminal of the battery. The FET transmits current towards the battery in response to the gate receiving the first control voltage, wherein the first control voltage is greater than the output voltage, and wherein the first control voltage is less than a breakdown voltage of the integrated circuit.
    Type: Application
    Filed: September 8, 2011
    Publication date: March 14, 2013
    Inventors: Tetsuo Sato, Tsutomu Kawano, Koji Kashimoto, Takao Hidaka, Tsuyoshi Ota, Ryoji Kato
  • Publication number: 20120262122
    Abstract: A battery management method and apparatus. In one embodiment of the method, a source current is divided into Ic and Icr. Ic is transmitted to and charges a battery. A first voltage is generated that is related to Icr. The first voltage is converted into a first digital signal. A processing unit receives and processes the first digital signal in accordance with instructions stored in a memory. The transmission of Ic to the battery is interrupted in response to the processing unit processing the first digital signal. Current provided by the battery is divided into Idc and Idcr. Idc is transmitted to a device. A second voltage is generated that is related to Idcr. The second voltage is converted into a second digital signal. The processing unit receives and processes the second digital signal in accordance with instructions stored in the memory. The transmission of Idc to the battery is interrupted in response to the processing unit processing the second digital signal.
    Type: Application
    Filed: April 18, 2011
    Publication date: October 18, 2012
    Inventors: Tetsuo Sato, Tsutomu Kawano, Koji Kashimoto, Takao Hidaka, Tsuyoshi Ota, Ryoji Kato
  • Publication number: 20090115934
    Abstract: A liquid crystal display includes a liquid crystal display panel for modulating light to form an image, and a back light unit having a plurality of lamp tubes with outside electrodes and without inside electrodes. Each of the plurality of lamp tubes has a first outside electrode disposed at one end portion and a second outside electrode disposed at another end portion. The first outside electrode which is disposed at one of the plurality of lamp tubes is electrically connected with the first outside electrode disposed at an adjacent another of the plurality of lamp tubes by a conductive member, and the second outside electrode which is disposed at the one of said plurality of lamp tubes is electrically connected with the second outside electrode disposed at the adjacent another of the plurality of lamp tubes by a conductive member.
    Type: Application
    Filed: January 2, 2009
    Publication date: May 7, 2009
    Inventors: Seiichi Nishiyama, Shigetake Takaku, Yoshiharu Takeda, Shigeo Mikoshiba, Tomokazu Shiga, Koji Kashimoto
  • Patent number: 6285539
    Abstract: In a switch driver, a pnp transistor turns ON or OFF the passage of the charging current. Resistors are commonly connected to a base of the pnp transistor. Npn transistors are provided in such a way that their collectors are connected to each of the resistors and their emitters are grounded. Bases of each of npn transistors are connected to a control unit. This control unit subsequently turns ON each of the npn transistors so that a base current required for turning ON the pnp transistor flows. Since the base current rises slowly, an abrupt rise of the switching current in a switch driver can be prevented.
    Type: Grant
    Filed: January 12, 2000
    Date of Patent: September 4, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Koji Kashimoto, Tomonori Tsuchiyama, Kazutaka Saito
  • Patent number: 5844645
    Abstract: A color LCD device is capable of preventing the leakage of an internal light irradiated from a back light without the problems relating to the fabrication cost and the cell-gap control. This device has a black matrix located and a light-shielding layer formed on a back surface of a color-filter substrate. The black matrix is located in a display area of the substrate. The light-shielding layer is located in a light-shielding area of the substrate. The black matrix is formed by a first part of a black layer located in the display area. The light-shielding layer is formed by a second part of the same layer located in the light-shielding area. At least one of red, green, and blue color-filter layers is formed as a continuous layer on substantially all of the light-shielding layer.
    Type: Grant
    Filed: June 20, 1997
    Date of Patent: December 1, 1998
    Assignee: NEC Corporation
    Inventor: Koji Kashimoto
  • Patent number: 5693978
    Abstract: A logic circuit (3) comprises IIL aggregates (4a, 4b, 4c) each consisting of a plurality of IIL elements. Each of the IIL aggregates (4a, 4b, 4c) is supplied with an injector current (I.sub.inj) from an injector current source (2) through a wiring (5). A monitoring element (6) is formed by utilizing an IIL element which needs the longest time until the injector current therein attains a predetermined value. When the injector current applied to an injector current input end (9) attains the predetermined value, potentials of an output terminal (10) and a reset signal input terminal (7) fall. Therefore, a reset operation is performed in accordance with the IIL element which needs the longest time until the injector current attains the predetermined value.
    Type: Grant
    Filed: March 5, 1997
    Date of Patent: December 2, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Koji Kashimoto
  • Patent number: 5600456
    Abstract: A transmission liquid crystal display comprises a liquid crystal panel including at least two substrates spaced apart from one another through spacers to confine a liquid crystal between the two substrates; a surface light source provided at a first side of the liquid crystal panel; and an optical diffusion lens having a plate-like shape provided at a second side of the liquid crystal panel, the lens having first and second surfaces, the first surface facing to a display screen and the second surface facing to a liquid crystal panel, entire parts of the first surface is flat, and the second surface comprises alternating flat portions and convex or concave portions having a predetermined curvature, the convex or concave portions having a difference in level of a top portion thereof from the flat portions, the convex or concave portions being arranged at a predetermined pitch, wherein a ratio of the difference in level to the pitch is in the range from 2.9:10 to 0.8:10.
    Type: Grant
    Filed: September 1, 1995
    Date of Patent: February 4, 1997
    Assignee: NEC Corporation
    Inventors: Muneo Maruyama, Koji Kashimoto
  • Patent number: 5585731
    Abstract: A test circuit for testing a current-voltage conversion amplifier having photodiode (PD) without actually exposing light to PD, including a current mirror circuit having a first NPN transistor and a second NPN transistor, an input terminal for applying a test voltage, a resistor connected between the input terminal and a collector of the first NPN transistor, and a current terminal connected to a collector of the second NPN transistor. The test circuit passes a current from the current-voltage conversion amplifier to the current terminal according to the test voltage which is applied to the input terminal.
    Type: Grant
    Filed: April 25, 1995
    Date of Patent: December 17, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuhito Tsuchida, Koji Kashimoto