Abstract: A clock generator contained in an integrated circuit has an input terminal, a first output terminal, and a second output terminal. When the input terminal of this clock generator receives a basic clock signal supplied by an external integrated circuit, the first output terminal outputs a first clock signal in response to the basic clock signal, and the second output terminal outputs a second clock signal which is an inverted clock signal of the first clock signal in response to the basic clock signal. When the input terminal receives a constant level signal supplied by the external integrated circuit, the first output terminal and the second output terminal output respectively the same constant level signal to thus provide reduced power consumption.

Abstract: A complementary semiconductor device includes P- and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. N-and P-channel type silicon gate field effect transistors are formed in the P-and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.

Abstract: A complementary semiconductor device includes P-and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. N-and P-channel type silicon gate field effect transistors are formed in the P-and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.

Abstract: A complementary semiconductor device includes P- and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. The N- and P-channel type silicon gate field effect transistors are formed in the P- and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.

Abstract: A liquid crystal display element-driving circuit wherein output signals from a decoder for decoding coded time data are supplied to a plurality of exclusive OR gates through the corresponding NAND gates; an output signal from a liquid crystal driving pulse generator is sent forth in common to the exclusive OR gates, and outputs from the respective exclusive OR gates are conducted to the corresponding segment electrodes of the liquid crystal display element, and which further comprises first and second logical level voltage-generating circuits; switch circuits controlled by said first and second logical level voltage-generating circuits, whereby all the segment electrodes can be impressed with voltage having the same logical level by means of said first and second logical level voltage-generating circuits and corresponding switch circuits.