Abstract: A semiconductor integrated circuit device is provided. The operating frequency generating component generates an operating frequency that is a timing that becomes a reference for synchronizing processing between each circuit when the semiconductor integrated circuit operates. The extracting component extracts a critical path that is the slowest path when a data signal propagates between predetermined terminals inside the semiconductor integrated circuit. The instruction prefetch executing component prefetches an instruction relating to the critical path that has been extracted by the extracting component. The processing configuration changing component changes the processing configuration so as to realize transmission of the data signal within a predetermined cycle of the operating frequency using the instruction prefetch executing component when the data signal passes through the path of the critical path.

Abstract: An apparatus which is tested includes a master logic unit and a slave logic unit. The testing method includes accessing a virtual slave logic unit by a test pattern which includes an address for accessing and an expected value of a waiting time, returning a response value from the virtual slave logic unit which is accessed by the address after lapse of the waiting time, and comparing the expected value and the response value.

Abstract: A phase adjustment circuit generates multiple clock signals by, for example, successively delaying a first clock signal. One of the generated clock signals is selected and output. A phase difference detector determines whether the phase of the selected clock signal and the phase of a second clock signal satisfy a given condition. The clock signal selection can changed until the condition is satisfied, either by external control by a device that monitors a signal output by the phase difference detector, or by a built-in selection signal generator. This scheme assures that two clock signals with phases satisfying the given condition are obtained, regardless of environmental factors or fabrication variations.

Abstract: An apparatus which is tested includes a master logic unit and a slave logic unit. The testing method includes accessing a virtual slave logic unit by a test pattern which includes an address for accessing and an expected value of a waiting time, returning a response value from the virtual slave logic unit which is accessed by the address after lapse of the waiting time, and comparing the expected value and the response value.

Abstract: A phase adjustment circuit generates multiple clock signals by, for example, successively delaying a first clock signal. One of the generated clock signals is selected and output. A phase difference detector determines whether the phase of the selected clock signal and the phase of a second clock signal satisfy a given condition. The clock signal selection can changed until the condition is satisfied, either by external control by a device that monitors a signal output by the phase difference detector, or by a built-in selection signal generator. This scheme assures that two clock signals with phases satisfying the given condition are obtained, regardless of environmental factors or fabrication variations.