Patents by Inventor Koji Nakahara
Koji Nakahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10927457Abstract: A semiconductor manufacturing apparatus in this embodiment includes a reactor, a pump, an exhaust pipe and a mesh member. The reactor houses a semiconductor substrate to treat the semiconductor substrate. The pump exhausts a gas inside the reactor. The exhaust pipe connects between the reactor and the pump. The mesh member is located at a flow inlet of the pump for the gas or in the exhaust pipe and has a main plane having a plurality of meshes arranged thereon. The mesh member has a protrusion and/or protruding shape projecting upstream of the gas.Type: GrantFiled: September 8, 2015Date of Patent: February 23, 2021Assignee: Toshiba Memory CorporationInventors: Koji Nakahara, Kazuhiro Matsuo
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Publication number: 20180277406Abstract: According to an embodiment, a substrate treatment apparatus includes a vacuum chamber, a cylindrical member, a gas feed member, a support member and a plurality of plate members. The cylindrical member is disposed in the vacuum chamber and includes a gas outlet. The support member supports a plurality of treated substrates in a stacked state in the cylindrical member. The plurality of plate members are supported on the support member and include a patterned surface or an outer circumferential part outside the treated substrate.Type: ApplicationFiled: September 8, 2017Publication date: September 27, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Koji NAKAHARA, Tomohisa IINO, Ryota FUJITSUKA
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Patent number: 9450108Abstract: A nonvolatile semiconductor memory device includes a semiconductor portion, a first oxygen-containing portion provided on the semiconductor portion, a silicon-containing portion provided on the first oxygen-containing portion, a first film provided on the silicon-containing portion and including a lamination of a first portion containing silicon and oxygen and a second portion containing silicon and nitrogen, a first high dielectric insulating portion provided on the first film and having an oxide-containing yttrium, hafnium or aluminum, a second oxygen-containing portion provided on the first high dielectric insulating portion, a second high dielectric insulating portion provided on the second oxygen-containing insulating portion and having an oxide-containing yttrium, hafnium or aluminum, a third oxygen-containing portion provided on the second high dielectric insulating portion, and a second film provided on the third oxygen-containing portion.Type: GrantFiled: April 27, 2015Date of Patent: September 20, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiro Matsuo, Masayuki Tanaka, Takeo Furuhata, Koji Nakahara
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Publication number: 20160258058Abstract: A semiconductor manufacturing apparatus in this embodiment includes a reactor, a pump, an exhaust pipe and a mesh member. The reactor houses a semiconductor substrate to treat the semiconductor substrate. The pump exhausts a gas inside the reactor. The exhaust pipe connects between the reactor and the pump. The mesh member is located at a flow inlet of the pump for the gas or in the exhaust pipe and has a main plane having a plurality of meshes arranged thereon. The mesh member has a protrusion and/or protruding shape projecting upstream of the gas.Type: ApplicationFiled: September 8, 2015Publication date: September 8, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koji Nakahara, Kazuhiro Matsuo
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Patent number: 9142685Abstract: A nonvolatile semiconductor memory device includes a semiconductor portion, a first oxygen-containing portion located on the semiconductor portion, a silicon-containing portion located on the first oxygen-containing portion, a first film located on the silicon-containing portion and including a lamination of a first portion containing silicon and oxygen and a second portion containing silicon and nitrogen, a first high dielectric insulating portion located on the first film and having an oxide-containing yttrium, hafnium or aluminum, a second oxygen-containing portion located on the first high dielectric insulating portion, a second high dielectric insulating portion located on the second oxygen-containing insulating portion and having an oxide-containing yttrium, hafnium or aluminum, a third oxygen-containing portion located on the second high dielectric insulating portion, and a second film located on the third oxygen-containing portion.Type: GrantFiled: May 8, 2014Date of Patent: September 22, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhiro Matsuo, Masayuki Tanaka, Takeo Furuhata, Koji Nakahara
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Publication number: 20150228662Abstract: A nonvolatile semiconductor memory device includes a semiconductor portion, a first oxygen-containing portion provided on the semiconductor portion, a silicon-containing portion provided on the first oxygen-containing portion, a first film provided on the silicon-containing portion and including a lamination of a first portion containing silicon and oxygen and a second portion containing silicon and nitrogen, a first high dielectric insulating portion provided on the first film and having an oxide-containing yttrium, hafnium or aluminum, a second oxygen-containing portion provided on the first high dielectric insulating portion, a second high dielectric insulating portion provided on the second oxygen-containing insulating portion and having an oxide-containing yttrium, hafnium or aluminum, a third oxygen-containing portion provided on the second high dielectric insulating portion, and a second film provided on the third oxygen-containing portion.Type: ApplicationFiled: April 27, 2015Publication date: August 13, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Kazuhiro MATSUO, Masayuki TANAKA, Takeo FURUHATA, Koji NAKAHARA
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Publication number: 20140239379Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, and a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film formed above the charge storage layer, a silicon nitride film formed on the first silicon oxide film, a metal oxide film formed on the silicon nitride film, and a nitride film formed on the metal oxide film. The metal oxide film has a relative permittivity of not less than 7.Type: ApplicationFiled: May 8, 2014Publication date: August 28, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Kazuhiro MATSUO, Masayuki TANAKA, Takeo FURUHATA, Koji NAKAHARA
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Patent number: 8791521Abstract: A semiconductor device includes an interelectrode insulating film formed between a charge storage layer and a control electrode layer. The interelectrode insulating film is formed in a first region above an upper surface of an element isolation insulating film, a second region along a sidewall of the charge storage layer, and a third region above an upper surface of the charge storage layer. The interelectrode insulating film includes a first stack including a first silicon nitride film or a high dielectric constant film interposed between a first and a second silicon oxide film or a second stack including a second high dielectric constant film and a third silicon oxide film, and a second silicon nitride film formed between the control electrode layer and the first or the second stack. The second silicon nitride film is relatively thinner in the third region than in the first region.Type: GrantFiled: March 19, 2012Date of Patent: July 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Koji Nakahara, Kazuhiro Matsuo, Masayuki Tanaka, Hirofumi Iikawa
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Patent number: 8742487Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer and including a first high dielectric insulating film which has a higher relative permittivity than a silicon nitride film and a second high dielectric insulating film which has a higher relative permittivity than a silicon nitride film, the first and second high dielectric insulating films being structured so that a silicon oxide film is interposed between them, a control electrode formed on the second insulation layer, a first portion formed between the charge storage layer and the second insulation layer and containing silicon and nitrogen, and a second portion containing silicon and oxygen and located between the charge storage layer and the second insulation layer.Type: GrantFiled: August 10, 2011Date of Patent: June 3, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiro Matsuo, Masayuki Tanaka, Takeo Furuhata, Koji Nakahara
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Patent number: 8471326Abstract: According to one embodiment, a semiconductor substrate includes a cell region and a peripheral circuit region, a first dielectric film is formed on the semiconductor substrate in the cell region and the peripheral circuit region, a first conductive film is formed on the first dielectric film in the cell region and the peripheral circuit region, a first inter-conductive-film dielectric film is formed on the first conductive film in the cell region, a second inter-conductive-film dielectric film is formed on the first conductive film in the peripheral circuit region and a film thickness thereof is larger than the first inter-conductive-film dielectric film, and a second conductive film is formed on the first inter-conductive-film dielectric film in the cell region and the second inter-conductive-film dielectric film in the peripheral circuit region.Type: GrantFiled: March 16, 2011Date of Patent: June 25, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Koji Nakahara, Kazuhiro Matsuo, Masayuki Tanaka
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Publication number: 20130069135Abstract: A semiconductor device includes an interelectrode insulating film formed between a charge storage layer and a control electrode layer. The interelectrode insulating film is formed in a first region above an upper surface of an element isolation insulating film, a second region along a sidewall of the charge storage layer, and a third region above an upper surface of the charge storage layer. The interelectrode insulating film includes a first stack including a first silicon nitride film or a high dielectric constant film interposed between a first and a second silicon oxide film or a second stack including a second high dielectric constant film and a third silicon oxide film, and a second silicon nitride film formed between the control electrode layer and the first or the second stack. The second silicon nitride film is relatively thinner in the third region than in the first region.Type: ApplicationFiled: March 19, 2012Publication date: March 21, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Koji Nakahara, Kazuhiro Matsuo, Masayuki Tanaka, Hirofumi Iikawa
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Publication number: 20130064553Abstract: An optical communication module comprising: a light emitting element to emit light; a light transmission medium to receive incidence of the light from the light emitting element; a diverging unit to be provided on the light transmission medium and to diverge some proportion of the light emitted from the light emitting element to the light transmission medium and propagating within the light transmission medium; and a first light receiving element to receive the light from the light emitting element, which is diverged by the diverging unit.Type: ApplicationFiled: September 11, 2012Publication date: March 14, 2013Applicant: FUJITSU LIMITEDInventor: Koji NAKAHARA
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Publication number: 20120049258Abstract: According to one embodiment, a semiconductor substrate includes a cell region and a peripheral circuit region, a first dielectric film is formed on the semiconductor substrate in the cell region and the peripheral circuit region, a first conductive film is formed on the first dielectric film in the cell region and the peripheral circuit region, a first inter-conductive-film dielectric film is formed on the first conductive film in the cell region, a second inter-conductive-film dielectric film is formed on the first conductive film in the peripheral circuit region and a film thickness thereof is larger than the first inter-conductive-film dielectric film, and a second conductive film is formed on the first inter-conductive-film dielectric film in the cell region and the second inter-conductive-film dielectric film in the peripheral circuit region.Type: ApplicationFiled: March 16, 2011Publication date: March 1, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Koji NAKAHARA, Kazuhiro Matsuo, Masayuki Tanaka
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Publication number: 20110298039Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, and a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film formed above the charge storage layer, a silicon nitride film formed on the first silicon oxide film, a metal oxide film formed on the silicon nitride film, and a nitride film formed on the metal oxide film. The metal oxide film has a relative permittivity of not less than 7.Type: ApplicationFiled: August 10, 2011Publication date: December 8, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhiro Matsuo, Masayuki Tanaka, Takeo Furuhata, Koji Nakahara
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Patent number: 8008707Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, and a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film formed above the charge storage layer, a silicon nitride film formed on the first silicon oxide film, a metal oxide film formed on the silicon nitride film, and a nitride film formed on the metal oxide film. The metal oxide film has a relative permittivity of not less than 7.Type: GrantFiled: December 12, 2008Date of Patent: August 30, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiro Matsuo, Masayuki Tanaka, Takeo Furuhata, Koji Nakahara
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Publication number: 20090152618Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film, an intermediate insulating film formed on the first silicon oxide film and having a relative permittivity of not less than 7, and a second silicon oxide film formed on the intermediate insulating film. A charge trap layer is formed at least in either first or second silicon oxide film or a boundary between the first silicon oxide film and the intermediate insulating film or a boundary between the second silicon oxide film and the intermediate insulating film.Type: ApplicationFiled: December 12, 2008Publication date: June 18, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhiro Matsuo, Masayuki Tanaka, Takeo Furuhata, Koji Nakahara
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Patent number: 7172659Abstract: The present invention is a production method of an R-T-B—C rare earth alloy (R is at least one element selected from the group consisting of rare earth elements and yttrium, T is a transition metal including iron as a main component, B is boron, and C is carbon). An R-T-B bonded magnet containing a resin component, or an R-T-B sintered magnet with a resin film formed on the surface thereof is prepared, and a solvent alloy containing a rare earth element R and a transition metal element T is prepared. Thereafter, the R-T-B bonded magnet is molten together with the solvent alloy. In this way, a rare earth alloy can be recovered from a spent bonded magnet or a defective one generated in a production process stage, and a rapidly quenched alloy magnet can be obtained. As a result, magnet powder is recovered from the R-T-B magnet, and the recycling of a magnet including a resin component can be realized.Type: GrantFiled: June 24, 2002Date of Patent: February 6, 2007Assignee: Neomax Co., Ltd.Inventors: Hiroyuki Tomizawa, Koji Nakahara, Yuji Kaneko
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Patent number: 6846754Abstract: A vapor-phase growth method for forming a boron-phosphide-based semiconductor layer on a single-crystal silicon (Si) substrate in a vapor-phase growth reactor. The method includes preliminary feeding of a boron (B)-containing gas, a phosphorus (P)-containing gas, and a carrier gas for carrying these gases into a vapor-phase growth reactor to thereby form a film containing boron and phosphorus on the inner wall of the vapor-phase growth reactor; and subsequently vapor-growing a boron-phosphide-based semiconductor layer on a single-crystal silicon substrate. Also disclosed is a boron-phosphide-based semiconductor layer prepared by the vapor-phase growth method.Type: GrantFiled: February 21, 2003Date of Patent: January 25, 2005Assignee: Showa Denko Kabushiki KaishaInventors: Takashi Udagawa, Koji Nakahara
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Publication number: 20040168746Abstract: The present invention is a production method of an R-T-B-C rare earth alloy (R is at least one element selected from the group consisting of rare earth elements and yttrium, T is a transition metal including iron as a main component, B is boron, and C is carbon). An R-T-B bonded magnet containing a resin component, or an R-T-B sintered magnet with a resin film formed on the surface thereof is prepared, and a solvent alloy containing a rare earth element R and a transition metal element T is prepared. Thereafter, the R-T-B bonded magnet is molten together with the solvent alloy. In this way, a rare earth alloy can be recovered from a spent bonded magnet or a defective one generated in a production process stage, and a rapidly quenched alloy magnet can be obtained. As a result, magnet powder is recovered from the R-T-B magnet, and the recycling of a magnet including a resin component can be realized.Type: ApplicationFiled: December 17, 2003Publication date: September 2, 2004Inventors: Hiroyuki Tomizawa, Koji Nakahara, Yuji Kaneko
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Publication number: 20030162371Abstract: A vapor-phase growth method for forming a boron-phosphide-based semiconductor layer on a single-crystal silicon (Si) substrate in a vapor-phase growth reactor. The method includes preliminary feeding of a boron (B)containing gas, a phosphorus (P)-containing gas, and a carrier gas for carrying these gases into a vapor-phase growth reactor to thereby form a film containing boron and phosphorus on the inner wall of the vapor-phase growth reactor; and subsequently vapor-growing a boron-phosphide-based semiconductor layer on a single-crystal silicon substrate. Also disclosed is a boron-phosphide-based semiconductor layer prepared by the vapor-phase growth method.Type: ApplicationFiled: February 21, 2003Publication date: August 28, 2003Applicant: SHOWA DENKO K.K.Inventors: Takashi Udagawa, Koji Nakahara