Abstract: The present invention relates to distributing the load between the set routes among a plurality of routes between a communication apparatus which serves as a start point to another communication apparatus which serves as an end point. An apparatus provided in a router in a network collects traffic characteristics of transmission paths connected to the router, notifies other routers of the collected traffic characteristics, calculates load based on the collected traffic characteristics, decides based on the calculated load information whether or not a transmission path should be added or deleted, and equalizes the load among the plurality of transmission paths.

Abstract: An L bit for notifying another router of whether a self-router belongs to a connection-oriented network is newly provided in the options field of a conventional OSPF packet and the OSPF packet, including L bit is transmitted to another router. In this way, each router belonging a network can automatically recognize a router belonging to a connection-oriented network by detecting L bit. Then, by generating a routing tree, a connection-oriented network device can be identified in the routing tree and mapping between a connection-oriented network and a connectionless network can be performed in an edge device.

Abstract: A packet flow control apparatus performing flow control of packets each having variable length, includes: a buffer memory for temporarily accumulating arrived packets until a sending time of each packet; a counter updated based on a rate determined in accordance with a packet length calculated by a counter value of the counter and limited flow of packets; a sending time determining section for determining the sending time of each packet based on the counter value and a present time; and a sending order control section for managing a sending order of each packet accumulated in the buffer memory, and for sending a read instruction of each packet to the buffer memory, based on the sending time determined by the sending time determining section.

Abstract: In a first UPC, a PCR is set as a monitor rate for each connection. If a transfer rate of a cell exceeds the PCR set for the connection, the cell is discarded. In a second UPC, an ACR is set as a monitor rate for each connection. If the transfer rate of the cell exceeds the ACR set for the connection, a lower priority is assigned to that cell. Additionally, with a configuration where one UPC monitors a varying rate, a parameter change process is controlled by obtaining a time between a passage time of a detected B-RM cell and an arrival of a user cell and comparing the obtained time with maximum and minimum delay standard values. A parameter table including some parameters is provided. A header of an arrived cell in a forward direction is extracted, and it is determined whether or not the arrived cell is a violation cell using the leaky bucket algorithm, etc. If the arrived cell is a violation cell, it is discarded.

Abstract: Specific ABR control capability for implementing an ABR service in an ATM switching system. A subscriber line processing device has a capability for calculating a turnaround delay time of a cell, based on a period during which the cell loops back at a terminal and returns. A switch or demultiplexer has a capability for detecting congestion. A rate calculator calculates a transmission rate corresponding to an output channel, and writes the calculated rate to the cell. A rate changer suitably changes the transmission rate according to the degree of occurrence of congestion. Additionally, the rate changer counts the number of communicating connections. At this time, the number of communicating connections which should exist in a certain predetermined period is estimated based on the counted number of communicating connections, which is counted in a period shorter than the predetermined period according to a predetermined method.

Abstract: An ATM connection is a virtual communication path specified by VPI/VCI. A plurality of ATM connections that are directed to the same output line is defined as an ATM connection group. A connection UPC (Usage Parameter Control) facility is provided for each of the ATM connections and a connection group UPC facility is provided for the ATM connection group. The connection UPC facilities and the connection group UPC facility are operated in either the monitor mode or the control mode. In the monitor mode, when the rate of flow of packets into a network exceeds a threshold, a control unit is informed of it, but cells are allowed to enter the network as they are. In the control mode, when the rate of flow of cells into the network exceeds the threshold, cells the flow rate of which exceeds the threshold are discarded.

Abstract: A feedback control apparatus whereby the traditional single control loop for available bit rate (ABR) connections is segmented into a plurality of loops that are handled in a mutually related manner for better responsiveness of ABR connection feedback control. Three control loops are illustratively formed: a closed upward feedback control loop between a source end system and a virtual destination-link unit (VD-L) for an ABR connection, a downward control loop between a destination end system and a virtual source-link unit (VS-L) for the ABR connection, and an intra-switch feedback control loop between an upstream virtual source-internal unit (VS-I) and a downstream virtual destination-internal unit (VD-I) for the ABR connection.

Abstract: A digital circuit design assist system is directed to provide a system which independently verifies hardware divided into a plurality of units or the hardware and software, and reduces the design time. The system includes a functional model storage unit 1 for storing functional models in order to design hardware for a desired digital circuit including the hardware alone or the hardware and firmware, and functionally expressing the digital circuit by a hardware description language through a text editor 15 by coding input. Logic synthesis system 2 is provided for converting the functional model to a structural model, structurally expressed by the hardware description language. Structural model storage unit 3 is provided for storing the structural model, and a language model library storage unit 4 is provided for storing language models each expressing each of a plurality of components constituting the hardware by the hardware description language.