Patents by Inventor Koji Nakamuta
Koji Nakamuta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9496966Abstract: A receiving device that converts, to a digital signal, a signal in which signal light from an optical transmission path and local oscillation light are mixed, so as to perform digital signal processing, the optical communication receiving device comprising: a frequency offset compensation unit configured to calculate a frequency offset of the digital signal and to, based on the frequency offset, compensate for a phase of the digital signal; a carrier phase recovery unit configured to calculate a carrier phase of the digital signal whose phase is compensated for in the frequency offset compensation unit; and a residual frequency offset detection unit configured to calculate an average of differences in the carrier phase, and to output the average as a residual frequency offset, wherein the frequency offset compensation unit is configured to correct the frequency offset using the residual frequency offset output by the residual frequency offset detection unit.Type: GrantFiled: September 24, 2014Date of Patent: November 15, 2016Assignee: FUJITSU LIMITEDInventors: Kazuhiko Hatae, Nobukazu Koizumi, Koji Nakamuta, Manabu Yamazaki, Tomoki Katou, Masashi Sato, Hisao Nakashima
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Patent number: 9444554Abstract: A digital coherent receiving apparatus includes a first oscillator for outputting a local light signal of a fixed frequency, a hybrid unit mixing the local light signal with a light signal received by a receiver, a second oscillator for outputting a sampling signal of a sampling frequency, a converter for converting the mixed light signal into digital signal synchronizing with the sampling signal, a waveform adjuster for adjusting a waveform distortion of the converted digital signal, a phase adjustor for adjusting a phase of the digital signal adjusted by the waveform adjustor, a demodulator for demodulating the digital signal adjusted by the phase adjuster, and a phase detector for detecting a phase of the digital signal adjusted by the phase adjuster, and a control signal output unit for outputting a frequency control signal on the basis of the detected phase signal to the second oscillator.Type: GrantFiled: September 27, 2013Date of Patent: September 13, 2016Assignee: FUJITSU LIMITEDInventors: Nobukazu Koizumi, Takeshi Hoshida, Takahito Tanimura, Hisao Nakashima, Koji Nakamuta, Noriyasu Nakayama
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Publication number: 20150098714Abstract: A receiving device that converts, to a digital signal, a signal in which signal light from an optical transmission path and local oscillation light are mixed, so as to perform digital signal processing, the optical communication receiving device comprising: a frequency offset compensation unit configured to calculate a frequency offset of the digital signal and to, based on the frequency offset, compensate for a phase of the digital signal; a carrier phase recovery unit configured to calculate a carrier phase of the digital signal whose phase is compensated for in the frequency offset compensation unit; and a residual frequency offset detection unit configured to calculate an average of differences in the carrier phase, and to output the average as a residual frequency offset, wherein the frequency offset compensation unit is configured to correct the frequency offset using the residual frequency offset output by the residual frequency offset detection unit.Type: ApplicationFiled: September 24, 2014Publication date: April 9, 2015Applicant: Fujitsu LimitedInventors: Kazuhiko HATAE, Nobukazu KOIZUMI, Koji NAKAMUTA, Manabu YAMAZAKI, Tomoki KATOU, Masashi SATO, Hisao NAKASHIMA
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Patent number: 8693898Abstract: An adaptive equalizer includes a finite impulse response filter with a predetermined number of taps; and a tap coefficient adaptive controller having a register to hold tap coefficients for the filter, a weighted center calculator to calculate a weighted center of the tap coefficients, and a tap coefficient shifter to shift the tap coefficients based on a calculation result of the weighted center. During an initial training period, the tap coefficient shifter shifts the tap coefficients on a symbol data basis such that a difference between the calculated weighted center of the tap coefficients and a tap center defined by the number of taps is minimized.Type: GrantFiled: October 14, 2011Date of Patent: April 8, 2014Assignee: Fujitsu LimitedInventors: Nobukazu Koizumi, Kazuhiko Hatae, Noriyasu Nakayama, Koji Nakamuta, Hisao Nakashima, Kosuke Komaki
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Patent number: 8649689Abstract: A digital coherent receiving apparatus includes a first oscillator for outputting a local light signal of a fixed frequency, a hybrid unit mixing the local light signal with a light signal received by a receiver, a second oscillator for outputting a sampling signal of a sampling frequency, a converter for converting the mixed light signal into digital signal synchronizing with the sampling signal, a waveform adjuster for adjusting a waveform distortion of the converted digital signal, a phase adjustor for adjusting a phase of the digital signal adjusted by the waveform adjustor, a demodulator for demodulating the digital signal adjusted by the phase adjuster, and a phase detector for detecting a phase of the digital signal adjusted by the phase adjuster, and a control signal output unit for outputting a frequency control signal on the basis of the detected phase signal to the second oscillator.Type: GrantFiled: June 22, 2010Date of Patent: February 11, 2014Assignee: Fujitsu LimitedInventors: Nobukazu Koizumi, Takeshi Hoshida, Takahito Tanimura, Hisao Nakashima, Koji Nakamuta, Noriyasu Nakayama
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Publication number: 20140029959Abstract: A digital coherent receiving apparatus includes a first oscillator for outputting a local light signal of a fixed frequency, a hybrid unit mixing the local light signal with a light signal received by a receiver, a second oscillator for outputting a sampling signal of a sampling frequency, a converter for converting the mixed light signal into digital signal synchronizing with the sampling signal, a waveform adjuster for adjusting a waveform distortion of the converted digital signal, a phase adjustor for adjusting a phase of the digital signal adjusted by the waveform adjustor, a demodulator for demodulating the digital signal adjusted by the phase adjuster, and a phase detector for detecting a phase of the digital signal adjusted by the phase adjuster, and a control signal output unit for outputting a frequency control signal on the basis of the detected phase signal to the second oscillator.Type: ApplicationFiled: September 27, 2013Publication date: January 30, 2014Applicant: FUJITSU LIMITEDInventors: Nobukazu KOIZUMI, Takeshi Hoshida, Takahito Tanimura, Hisao Nakashima, Koji Nakamuta, Noriyasu Nakayama
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Publication number: 20130241610Abstract: A PLL circuit includes a digital PLL circuit and an analog PLL circuit, wherein the digital PLL circuit includes a first digital phase detector configured to detect a first phase difference between a reference clock signal and a first feedback clock signal, and a phase accumulator configured to generate, as the first feedback clock signal, a digital oscillating signal having oscillating frequency that changes in response to the detected first phase difference, and wherein the analog PLL circuit includes a second digital phase detector configured to detect a second phase difference between the digital oscillating signal generated by the phase accumulator and a second feedback clock signal, and a voltage controlled oscillator configured to receive a voltage value changing in response to the detected second phase difference and to generate the second feedback clock signal that oscillates at frequency responsive to the voltage value.Type: ApplicationFiled: January 8, 2013Publication date: September 19, 2013Inventors: Koji NAKAMUTA, Yoshito Koyama
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Patent number: 8536911Abstract: A PLL circuit includes a digital PLL circuit and an analog PLL circuit, wherein the digital PLL circuit includes a first digital phase detector configured to detect a first phase difference between a reference clock signal and a first feedback clock signal, and a phase accumulator configured to generate, as the first feedback clock signal, a digital oscillating signal having oscillating frequency that changes in response to the detected first phase difference, and wherein the analog PLL circuit includes a second digital phase detector configured to detect a second phase difference between the digital oscillating signal generated by the phase accumulator and a second feedback clock signal, and a voltage controlled oscillator configured to receive a voltage value changing in response to the detected second phase difference and to generate the second feedback clock signal that oscillates at frequency responsive to the voltage value.Type: GrantFiled: January 8, 2013Date of Patent: September 17, 2013Assignee: Fujitsu LimitedInventors: Koji Nakamuta, Yoshito Koyama
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Patent number: 8488062Abstract: An apparatus includes a voltage controlled oscillator for outputting a clock signal having an oscillation frequency in accordance with an input voltage; a convertor for converting the analog video signal inputted from the exterior into the digital video signal synchronizing with the clock signal outputted from the voltage controlled oscillator; a phase difference detector for detecting a phase difference between the composite synchronizing signal in the analog video signal and a feedback signal which corresponds to the clock signal from the voltage-controlled oscillator; and a voltage control unit for controlling the input voltage of the voltage controlled oscillator to change in response to the phase difference detected by the phase difference detector when the phase difference is within the certain range, and to maintain the input voltage intact when the phase difference is in exceed of the certain range.Type: GrantFiled: March 9, 2010Date of Patent: July 16, 2013Assignee: Fujitsu LimitedInventors: Koji Nakamuta, Yoshito Koyama
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Patent number: 8436665Abstract: A digital PLL circuit includes: a digital phase comparator to detect a phase difference between a master clock and a slave clock and output a phase difference detection value; a correction circuit to correct the phase difference detection value to a phase value in accordance with a comparison result between the phase difference detection value and a threshold; and a slave clock generation circuit to generate the slave clock in accordance with the phase value.Type: GrantFiled: March 13, 2012Date of Patent: May 7, 2013Assignee: Fujitsu LimitedInventors: Koji Nakamuta, Yoshito Koyama
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Publication number: 20130063183Abstract: A signal generating apparatus includes: a direct digital synthesizer configured to generate an output signal of a frequency according to first control data based on a reference clock; and a controller configured to provide the direct digital synthesizer with the first control data at a timing synchronized with the reference clock, wherein the controller includes a table which stores second setting data for controlling the frequency of the output signal based on jitter information and provides the direct digital synthesizer with the second setting data in the table as the first control data at the timing.Type: ApplicationFiled: July 30, 2012Publication date: March 14, 2013Applicant: FUJITSU LIMITEDInventors: Yoshinori Nakane, Yoshito Koyama, Koji Nakamuta
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Publication number: 20120242386Abstract: A digital PLL circuit includes: a digital phase comparator to detect a phase difference between a master clock and a slave clock and output a phase difference detection value; a correction circuit to correct the phase difference detection value to a phase value in accordance with a comparison result between the phase difference detection value and a threshold; and a slave clock generation circuit to generate the slave clock in accordance with the phase value.Type: ApplicationFiled: March 13, 2012Publication date: September 27, 2012Applicant: Fujitsu LimitedInventors: Koji Nakamuta, Yoshito Koyama
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Publication number: 20120134684Abstract: An adaptive equalizer includes a finite impulse response filter with a predetermined number of taps; and a tap coefficient adaptive controller having a register to hold tap coefficients for the filter, a weighted center calculator to calculate a weighted center of the tap coefficients, and a tap coefficient shifter to shift the tap coefficients based on a calculation result of the weighted center. During an initial training period, the tap coefficient shifter shifts the tap coefficients on a symbol data basis such that a difference between the calculated weighted center of the tap coefficients and a tap center defined by the number of taps is minimized.Type: ApplicationFiled: October 14, 2011Publication date: May 31, 2012Applicant: FUJITSU LIMITEDInventors: Nobukazu Koizumi, Kazuhiko Hatae, Noriyasu Nakayama, Koji Nakamuta, Hisao Nakashima, Kosuke Komaki
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Patent number: 8183940Abstract: A thermostatic-chamber temperature control device includes: a heating element for heating a thermostatic chamber; a bridge circuit having a temperature sensitive element whose resistance value varies in accordance with the temperature of the heating element; a detection circuit for detecting an unbalanced voltage of the bridge circuit; a PWM signal generating circuit for generating a PWM signal corresponding to the unbalanced voltage detected by the detection circuit; and a switching element that has a current output terminal connected to the heating element and a current input terminal connected to a power supply circuit and is driven on the basis of the PWM signal generated by the PWM signal generating circuit.Type: GrantFiled: August 28, 2009Date of Patent: May 22, 2012Assignee: Fujitsu LimitedInventors: Yoshito Koyama, Minoru Hirahara, Koji Nakamuta
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Publication number: 20100329697Abstract: A digital coherent receiving apparatus includes a first oscillator for outputting a local light signal of a fixed frequency, a hybrid unit mixing the local light signal with a light signal received by a receiver, a second oscillator for outputting a sampling signal of a sampling frequency, a converter for converting the mixed light signal into digital signal synchronizing with the sampling signal, a waveform adjuster for adjusting a waveform distortion of the converted digital signal, a phase adjustor for adjusting a phase of the digital signal adjusted by the waveform adjustor, a demodulator for demodulating the digital signal adjusted by the phase adjuster, and a phase detector for detecting a phase of the digital signal adjusted by the phase adjuster, and a control signal output unit for outputting a frequency control signal on the basis of the detected phase signal to the second oscillator.Type: ApplicationFiled: June 22, 2010Publication date: December 30, 2010Applicant: FUJITSU LIMITEDInventors: Nobukazu KOIZUMI, Takeshi Hoshida, Takahito Tanimura, Hisao Nakashima, Koji Nakamuta, Noriyasu Nakayama
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Publication number: 20100231789Abstract: An apparatus includes a voltage controlled oscillator for outputting a clock signal having an oscillation frequency in accordance with an input voltage; a convertor for converting the analog video signal inputted from the exterior into the digital video signal synchronizing with the clock signal outputted from the voltage controlled oscillator; a phase difference detector for detecting a phase difference between the composite synchronizing signal in the analog video signal and a feedback signal which corresponds to the clock signal from the voltage-controlled oscillator; and a voltage control unit for controlling the input voltage of the voltage controlled oscillator to change in response to the phase difference detected by the phase difference detector when the phase difference is within the certain range, and to maintain the input voltage intact when the phase difference is in exceed of the certain range.Type: ApplicationFiled: March 9, 2010Publication date: September 16, 2010Applicant: FUJITSU LIMITEDInventors: Koji NAKAMUTA, Yoshito KOYAMA
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Publication number: 20100052801Abstract: A thermostatic-chamber temperature control device includes: a heating element for heating a thermostatic chamber; a bridge circuit having a temperature sensitive element whose resistance value varies in accordance with the temperature of the heating element; a detection circuit for detecting an unbalanced voltage of the bridge circuit; a PWM signal generating circuit for generating a PWM signal corresponding to the unbalanced voltage detected by the detection circuit; and a switching element that has a current output terminal connected to the heating element and a current input terminal connected to a power supply circuit and is driven on the basis of the PWM signal generated by the PWM signal generating circuit.Type: ApplicationFiled: August 28, 2009Publication date: March 4, 2010Applicant: FUJITSU LIMITEDInventors: Yoshito Koyama, Minoru Hirahara, Koji Nakamuta
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Patent number: 7664217Abstract: A DPLL circuit is provided for making it possible to inhibit an initial frequency offset during holdover. The DPLL circuit includes a slave oscillator for generating a frequency signal corresponding to the size of a control signal value; a phase difference detection circuit for detecting the difference in phase between the output of said slave oscillator and the inputted reference clock, and outputting a digital signal of the prescribed number of bits corresponding to said detected phase difference; and a holdover unit for generating a correction value based on the output of said phase difference detection circuit, wherein when the holdover is detected, said holdover unit periodically adds the correction value to the output of said phase difference detection circuit to obtain a control value for said slave oscillator.Type: GrantFiled: June 10, 2005Date of Patent: February 16, 2010Assignee: Fujitsu LimitedInventors: Koji Nakamuta, Yoshito Koyama
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Publication number: 20090295490Abstract: A circuit includes a DDS unit deriving a sine wave from a tuning word using a frequency of a reference clock, a first frequency divider dividing the frequency of the reference clock, a second frequency divider dividing a frequency of the sine wave output by the DDS unit, and a mixer mixing the sine wave of a divided frequency with the reference clock of a divided frequency to thus produce the sine wave of a mixed frequency.Type: ApplicationFiled: February 5, 2009Publication date: December 3, 2009Applicant: FUJITSU LIMITEDInventors: Koji NAKAMUTA, Yoshito KOYAMA
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Patent number: 7417477Abstract: To a frequency divider having a reset function, a second clock of a frequency N×Y times higher than that of a first clock is inputted. Upon receipt of a signal indicating that the stop of the input clock is detected by a start/stop detection circuit, the frequency divider having a reset function resets the dividing of a frequency. Then, upon receipt of a signal indicating that the resumption of the input clock is detected by the start/stop detection circuit, the frequency divider generates and inputs a third clock to a phase comparator by starting the dividing of a frequency.Type: GrantFiled: February 1, 2007Date of Patent: August 26, 2008Assignee: Fujitsu LimitedInventors: Yoshito Koyama, Koji Nakamuta