Abstract: A rectification circuit has a first terminal to which an alternating-current voltage is input from an antenna, a second terminal to which a direct-current voltage is input from the antenna, a first rectification element, a second rectification element, and a voltage rectification circuit. The first rectification element is connected between the first terminal and the second terminal, causes a current to flow in a first direction from the first terminal to the second terminal, and cuts off a current in a second direction from the second terminal to the first terminal. The second rectification element is connected between the first terminal and the second terminal, causes a current to flow in the second direction, and cuts off a current in the first direction. The voltage rectification circuit outputs a rectified voltage obtained by rectifying a voltage that is input between the first terminal and the second terminal.

Abstract: A multi-panel joint assembly, joint and method for a vehicle includes a first panel forming an outer skin on the vehicle, a second panel having a second panel flange portion overlapping the first panel, a third panel having a third panel flange portion overlapping the second panel flange portion, throughholes in registry with one another defined respectively in the first panel, the second panel flange portion, and the third panel flange portion, a rivet nut received through the throughole of the first panel, a fastener received through the throughholes of the second and third panels and threadedly secured to the rivet nut for securing the second and third panels to the first panel, and a washer interposed between the first panel and a deformed portion of the rivet nut for protecting the first panel from being damaged by the deformed portion.

Abstract: A multi-panel joint assembly, joint and method for a vehicle includes a first panel forming an outer skin on the vehicle, a second panel having a second panel flange portion overlapping the first panel, a third panel having a third panel flange portion overlapping the second panel flange portion, througholes in registry with one another defined respectively in the first panel, the second panel flange portion, and the third panel flange portion, a rivet nut received through the throughole of the first panel, a fastener received through the througholes of the second and third panels and threadedly secured to the rivet nut for securing the second and third panels to the first panel, and a washer interposed between the first panel and a deformed portion of the rivet nut for protecting the first panel from being damaged by the deformed portion.

Abstract: A rectification circuit has a first terminal to which an alternating-current voltage is input from an antenna, a second terminal to which a direct-current voltage is input from the antenna, a first rectification element, a second rectification element, and a voltage rectification circuit. The first rectification element is connected between the first terminal and the second terminal, causes a current to flow in a first direction from the first terminal to the second terminal, and cuts off a current in a second direction from the second terminal to the first terminal. The second rectification element is connected between the first terminal and the second terminal, causes a current to flow in the second direction, and cuts off a current in the first direction. The voltage rectification circuit outputs a rectified voltage obtained by rectifying a voltage that is input between the first terminal and the second terminal.

Abstract: A semiconductor integrated circuit includes a substrate, an oxide layer formed on an upper surface of the substrate, a plurality of polysilicon members arranged at constant intervals in a matrix on an upper surface of the oxide layer and including at least one first polysilicon member and a plurality of second polysilicon members, and a diffusion layer formed in the substrate under the first polysilicon member and electrically coupled to an interconnect for supplying a first power supply voltage, wherein the first polysilicon member is situated at an outermost periphery of the matrix and electrically coupled to an interconnect for supplying a second power supply voltage, and the plurality of second polysilicon members are situated inside the outermost periphery of the matrix.

Abstract: A semiconductor integrated circuit includes a substrate, an oxide layer formed on an upper surface of the substrate, a plurality of polysilicon members arranged at constant intervals in a matrix on an upper surface of the oxide layer and including at least one first polysilicon member and a plurality of second polysilicon members, and a diffusion layer formed in the substrate under the first polysilicon member and electrically coupled to an interconnect for supplying a first power supply voltage, wherein the first polysilicon member is situated at an outermost periphery of the matrix and electrically coupled to an interconnect for supplying a second power supply voltage, and the plurality of second polysilicon members are situated inside the outermost periphery of the matrix.

Abstract: Aspects of the embodiment provide a semiconductor integrated circuit including a control terminal coupled to a memory through a control bus, a data terminal coupled to the memory through a data bus, a memory controller coupled to the control terminal and the data terminal and a first master and a second master coupled to the memory controller, wherein the memory controller supplies a control signal corresponding to a memory access based on the first master and a control signal corresponding to a memory access based on the second master to the control terminal in synchronism with a rising edge and a falling edge of a clock signal, respectively, and the memory controller receives and outputs input/output data of the first master and input/output data of the second master at the data terminal in synchronism with the rising edge and the falling edge, respectively.

Abstract: A semiconductor integrated circuit includes a substrate, an oxide layer formed on an upper surface of the substrate, a plurality of polysilicon members arranged at constant intervals in a matrix on an upper surface of the oxide layer and including at least one first polysilicon member and a plurality of second polysilicon members, and a diffusion layer formed in the substrate under the first polysilicon member and electrically coupled to an interconnect for supplying a first power supply voltage, wherein the first polysilicon member is situated at an outermost periphery of the matrix and electrically coupled to an interconnect for supplying a second power supply voltage, and the plurality of second polysilicon members are situated inside the outermost periphery of the matrix.

Abstract: Aspects of the embodiment provide a semiconductor integrated circuit including a control terminal coupled to a memory through a control bus, a data terminal coupled to the memory through a data bus, a memory controller coupled to the control terminal and the data terminal and a first master and a second master coupled to the memory controller, wherein the memory controller supplies a control signal corresponding to a memory access based on the first master and a control signal corresponding to a memory access based on the second master to the control terminal in synchronism with a rising edge and a falling edge of a clock signal, respectively, and the memory controller receives and outputs input/output data of the first master and input/output data of the second master at the data terminal in synchronism with the rising edge and the falling edge, respectively.

Abstract: A filter circuit, having a plurality of selectable impedance elements, that has a cutoff frequency dependent on a selected impedance element, comprises a pulse generation circuit that supplies a variable frequency pulse with a successively increasing or decreasing frequency to an input of the filter circuit; and an impedance element selection unit that checks the attenuation of the output pulse of the filter circuit corresponding with the input of the variable frequency pulse and selects the plurality of impedance elements on the basis of the position of a pulse that is attenuated to or below a reference value.

Abstract: A filter circuit, having a plurality of selectable impedance elements, that has a cutoff frequency dependent on a selected impedance element, comprises a pulse generation circuit that supplies a variable frequency pulse with a successively increasing or decreasing frequency to an input of the filter circuit; and an impedance element selection unit that checks the attenuation of the output pulse of the filter circuit corresponding with the input of the variable frequency pulse and selects the plurality of impedance elements on the basis of the position of a pulse that is attenuated to or below a reference value.