Patents by Inventor Koji Ogiso
Koji Ogiso has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230345838Abstract: A piezoelectric element that includes: a piezoelectric ceramic containing, as a main component thereof, a composite oxide having a perovskite crystal structure; a first electrode on a first face of the piezoelectric ceramic; and a second electrode on a second face of the piezoelectric ceramic opposite the first face. The piezoelectric ceramic mainly has a rhombohedral crystal structure. The crystal axis of the piezoelectric ceramic is {100} oriented, and the direction of the {100} orientation is orthogonal to the direction in which the first electrode and the second electrode face each other.Type: ApplicationFiled: June 30, 2023Publication date: October 26, 2023Inventors: Koji OGISO, Yasunari MIWA, Hideki ISHII, Daisuke KURODA
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Patent number: 10720410Abstract: A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor substrate, a second metal layer located on the second semiconductor substrate, a third metal layer, a first alloy layer, and a second alloy layer. The third metal layer extends between the first metal layer and the second metal layer. The first alloy layer comprises components of the first and third metal layers, and is provided between the first metal layer and the third metal layer. The second alloy layer comprises components of the second and third metal layers, and is provided between the second metal layer and the third metal layer. At least one of the first metal the second metal layers projects into the third metal layer at a circumferential edge portion thereof.Type: GrantFiled: September 7, 2018Date of Patent: July 21, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tatsuo Migita, Koji Ogiso
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Patent number: 10312143Abstract: A semiconductor device includes a semiconductor substrate, a metal member, and a metal oxide film. The semiconductor substrate is provided with a through-hole that passes through the semiconductor substrate from one surface to another surface opposite to the one surface. The metal member is provided in the through-hole, and includes a cavity therein defined by an internal surface. The metal oxide film coats the internal surface.Type: GrantFiled: March 4, 2016Date of Patent: June 4, 2019Assignee: Toshiba Memory CorporationInventors: Tatsuo Migita, Koji Ogiso
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Publication number: 20190006324Abstract: A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor substrate, a second metal layer located on the second semiconductor substrate, a third metal layer, a first alloy layer, and a second alloy layer. The third metal layer extends between the first metal layer and the second metal layer. The first alloy layer comprises components of the first and third metal layers, and is provided between the first metal layer and the third metal layer. The second alloy layer comprises components of the second and third metal layers, and is provided between the second metal layer and the third metal layer. At least one of the first metal the second metal layers projects into the third metal layer at a circumferential edge portion thereof.Type: ApplicationFiled: September 7, 2018Publication date: January 3, 2019Inventors: Tatsuo MIGITA, Koji OGISO
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Patent number: 10115703Abstract: A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor substrate, a second metal layer located on the second semiconductor substrate, a third metal layer, a first alloy layer, and a second alloy layer. The third metal layer extends between the first metal layer and the second metal layer. The first alloy layer comprises components of the first and third metal layers, and is provided between the first metal layer and the third metal layer. The second alloy layer comprises components of the second and third metal layers, and is provided between the second metal layer and the third metal layer. At least one of the first metal the second metal layers projects into the third metal layer at a circumferential edge portion thereof.Type: GrantFiled: March 3, 2016Date of Patent: October 30, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tatsuo Migita, Koji Ogiso
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Patent number: 10083893Abstract: According to an embodiment, a semiconductor device is provided. The semiconductor device includes a through-hole, a copper layer, and a metal portion. The through-hole penetrates a semiconductor substrate between front and rear sides. The copper layer is formed inside the through-hole. The metal portion is made of a metal other than copper, formed closer to a hole core side of the through-hole than the copper layer is, and involves a void therein.Type: GrantFiled: September 10, 2014Date of Patent: September 25, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Koji Ogiso, Kazuyuki Higashi, Tatsuo Migita
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Patent number: 9941165Abstract: A semiconductor manufacturing method includes forming a first metal film on a semiconductor wafer by plating, ejecting liquid from a washer bar spaced from the wafer while rotating at least one of the washer and the semiconductor, and forming a second metal film on the first metal film. A plurality of nozzles are located on the washer bar and displaced from the position of the washer bar opposed to the center of the wafer, and a greater number of nozzles are adjacent the peripheral area of the semiconductor wafer than the central area of the semiconductor wafer. The nozzles in the peripheral area of the wafer eject the washing liquid in a direction inclined from the direction of the washer bar, and a nozzle arranged on the central area of the one main surface of the semiconductor wafer ejects the washing liquid towards the center position of the semiconductor wafer.Type: GrantFiled: August 8, 2016Date of Patent: April 10, 2018Assignee: Toshiba Memory CorporationInventors: Tatsuo Migita, Fumito Shoji, Koji Ogiso
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Patent number: 9893036Abstract: A semiconductor device includes a first substrate, an aluminum pad, a first nickel electrode, a second substrate, a second nickel electrode, and a connection layer. The first substrate includes a wiring therein. The aluminum pad is provided adjacent to a surface layer of the first substrate and is connected to the wiring. A portion of the first nickel electrode extends inwardly of the first substrate and is connected to the aluminum pad. A top surface of the first nickel electrode projects from a surface of the first substrate. A portion of the second nickel electrode extends inwardly of the second substrate. A top surface of the second nickel electrode projects from a surface of the second substrate facing the first substrate. The connection layer comprises an alloy including tin and connects the first nickel electrode and the second nickel electrode.Type: GrantFiled: March 3, 2016Date of Patent: February 13, 2018Assignee: Toshiba Memory CorporationInventors: Koji Ogiso, Kazuhiro Murakami, Tatsuo Migita
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Publication number: 20170263499Abstract: A semiconductor manufacturing method includes forming a first metal film on a semiconductor wafer by plating, ejecting liquid from a washer bar spaced from the wafer while rotating at least one of the washer and the semiconductor, and forming a second metal film on the first metal film. A plurality of nozzles are located on the washer bar and displaced from the position of the washer bar opposed to the center of the wafer, and a greater number of nozzles are adjacent the peripheral area of the semiconductor wafer than the central area of the semiconductor wafer. The nozzles in the peripheral area of the wafer eject the washing liquid in a direction inclined from the direction of the washer bar, and a nozzle arranged on the central area of the one main surface of the semiconductor wafer ejects the washing liquid towards the center position of the semiconductor wafer.Type: ApplicationFiled: August 8, 2016Publication date: September 14, 2017Inventors: Tatsuo MIGITA, Fumito SHOJI, Koji OGISO
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Publication number: 20160351450Abstract: A semiconductor device includes a semiconductor substrate, a metal member, and a metal oxide film. The semiconductor substrate is provided with a through-hole that passes through the semiconductor substrate from one surface to another surface opposite to the one surface. The metal member is provided in the through-hole, and includes a cavity therein defined by an internal surface. The metal oxide film coats the internal surface.Type: ApplicationFiled: March 4, 2016Publication date: December 1, 2016Inventors: Tatsuo MIGITA, Koji OGISO
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Publication number: 20160351540Abstract: A semiconductor device includes a first substrate, an aluminum pad, a first nickel electrode, a second substrate, a second nickel electrode, and a connection layer. The first substrate includes a wiring therein. The aluminum pad is provided adjacent to a surface layer of the first substrate and is connected to the wiring. A portion of the first nickel electrode extends inwardly of the first substrate and is connected to the aluminum pad. A top surface of the first nickel electrode projects from a surface of the first substrate. A portion of the second nickel electrode extends inwardly of the second substrate. A top surface of the second nickel electrode projects from a surface of the second substrate facing the first substrate. The connection layer comprises an alloy including tin and connects the first nickel electrode and the second nickel electrode.Type: ApplicationFiled: March 3, 2016Publication date: December 1, 2016Inventors: Koji OGISO, Kazuhiro MURAKAMI, Tatsuo MIGITA
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Publication number: 20160276299Abstract: A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor substrate, a second metal layer located on the second semiconductor substrate, a third metal layer, a first alloy layer, and a second alloy layer. The third metal layer extends between the first metal layer and the second metal layer. The first alloy layer comprises components of the first and third metal layers, and is provided between the first metal layer and the third metal layer. The second alloy layer comprises components of the second and third metal layers, and is provided between the second metal layer and the third metal layer. At least one of the first metal the second metal layers projects into the third metal layer at a circumferential edge portion thereof.Type: ApplicationFiled: March 3, 2016Publication date: September 22, 2016Inventors: Tatsuo MIGITA, Koji OGISO
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Publication number: 20160035624Abstract: According to one embodiment, a semiconductor device manufacturing method provides filling a through-hole which penetrates through a first side of substrate to a second side thereof. A seed film including copper is formed on the inner wall surface of the through-hole. A first metal layer including copper is grown bottom-up from one end of the through-hole toward the other end thereof, to partially fill the through-hole, leaving a space having a depth less than the radius of the through-hole as measured from the second side surface of the substrate. A second metal layer including nickel is conformally grown in the space from the inner peripheral surface of the through-hole to a height having a summit surface protruding from the second side surface of the substrate. A third metal layer is formed on the summit surface of the second metal layer.Type: ApplicationFiled: October 15, 2015Publication date: February 4, 2016Inventors: Koji OGISO, Soichi YAMASHITA, Kazuhiro MURAKAMI
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Publication number: 20150214134Abstract: According to an embodiment, a semiconductor device is provided. The semiconductor device includes a through-hole, a copper layer, and a metal portion. The through-hole penetrates a semiconductor substrate between front and rear sides. The copper layer is formed inside the through-hole. The metal portion is made of a metal other than copper, formed closer to a hole core side of the through-hole than the copper layer is, and involves a void therein.Type: ApplicationFiled: September 10, 2014Publication date: July 30, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Koji OGISO, Kazuyuki HIGASHI, Tatsuo MIGITA
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Publication number: 20140284772Abstract: According to one embodiment, a semiconductor device manufacturing method provides filling a through-hole which penetrates through a first side of substrate to a second side thereof. A seed film including copper is formed on the inner wall surface of the through-hole. A first metal layer including copper is grown bottom-up from one end of the through-hole toward the other end thereof, to partially fill the through-hole, leaving a space having a depth less than the radius of the through-hole as measured from the second side surface of the substrate. A second metal layer including nickel is conformally grown in the space from the inner peripheral surface of the through-hole to a height having a summit surface protruding from the second side surface of the substrate. A third metal layer is formed on the summit surface of the second metal layer.Type: ApplicationFiled: August 30, 2013Publication date: September 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koji OGISO, Soichi YAMASHITA, Kazuhiro MURAKAMI
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Patent number: 8191758Abstract: In one embodiment, a first substrate having first solder bumps and a second substrate having second solder bumps are stacked while temporarily tacking the solder bumps to each other, and then a stack is disposed inside a furnace. The gas in the furnace is exhausted to be in a reduced pressure atmosphere, and then a carboxylic acid gas is introduced into the furnace. While increasing a temperature inside the furnace where the carboxylic acid gas is introduced, the gas in the furnace is exhausted to be in a reduced pressure atmosphere at a temperature in a range from a reduction temperature of oxide films by the carboxylic acid gas to lower than a melting temperature of the solder bumps. By increasing the temperature inside the furnace up to a temperature in a range of the melting temperature of the solder bumps and higher, the first solder bumps and the second solder bumps are melted and joined.Type: GrantFiled: June 15, 2010Date of Patent: June 5, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Kanako Sawada, Hideo Aoki, Naoyuki Komuta, Koji Ogiso
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Publication number: 20120018920Abstract: According to one embodiment, a resin supply device is configured to supply granular resins to a resin mold device including a first mold provided with a cavity and a second mold mated to the first mold. The resin supply device includes a first mechanism and a second mechanism. The first mechanism is configured to juxtapose multiple granular resins on an adsorption surface by adsorbing the multiple granular resins on the adsorption surface larger than the granular resins, and form an adsorbed resin body with a uniform thickness. The adsorbed resin body is made of the adsorbed multiple granular resins on the adsorption surface. The second mechanism is configured to drop the multiple granular resins adsorbed on the adsorption surface into the cavity by adsorption-release of the adsorption surface.Type: ApplicationFiled: July 12, 2011Publication date: January 26, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Koji OGISO, Taku Kamoto
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Publication number: 20100320258Abstract: In one embodiment, a first substrate having first solder bumps and a second substrate having second solder bumps are stacked while temporarily tacking the solder bumps to each other, and then a stack is disposed inside a furnace. The gas in the furnace is exhausted to be in a reduced pressure atmosphere, and then a carboxylic acid gas is introduced into the furnace. While increasing a temperature inside the furnace where the carboxylic acid gas is introduced, the gas in the furnace is exhausted to be in a reduced pressure atmosphere at a temperature in a range from a reduction temperature of oxide films by the carboxylic acid gas to lower than a melting temperature of the solder bumps. By increasing the temperature inside the furnace up to a temperature in a range of the melting temperature of the solder bumps and higher, the first solder bumps and the second solder bumps are melted and joined.Type: ApplicationFiled: June 15, 2010Publication date: December 23, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kanako Sawada, Hideo Aoki, Naoyuki Komuta, Koji Ogiso
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Patent number: 7808155Abstract: A monolithic piezoelectric element includes an element assembly in which internal electrode layers and piezoelectric ceramic layers are laminated alternately. The internal electrode layers contain an Ag—Pd alloy, which has an Ag content of 85 percent by weight or more as a primary component, a metal element having a valence of at least one of pentavalence or hexavalence. The piezoelectric ceramic layers contain a composite oxide represented by Pb(Ti,Zr)O3 as a primary component, a part of Ag contained in the internal electrode layers is almost uniformly diffused therein and, the metal element is diffused in the form of a metal oxide in such a way that the concentration is reduced with decreasing proximity to the internal electrode layers. In this manner, a monolithic piezoelectric element having a desired large piezoelectric constant can be obtained without inviting an increase in cost even when a firing treatment is conducted at low temperatures.Type: GrantFiled: June 4, 2009Date of Patent: October 5, 2010Assignee: Murata Manufacturing Co., Ltd.Inventors: Atsushi Yamamoto, Koji Ogiso, Koichi Hayashi
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Patent number: 7595006Abstract: A piezoelectric ceramic composition has the composition formula (Pb(a-b)Meb){(Ni(1-c).d/3Znc.d/3Nb2/3)zTixZr(1-x-z)}O3, wherein Me represents at least one element selected from the group consisting of Ba, Sr and Ca; a, b, c, d, x and z satisfy the inequalities 0.975?a?0.998, 0?b?0.05, 1<d?1.40, and 0.39?x?0.47; and c and z are located in a region surrounded by lines connecting Point A (z=0.25, c=0.1), Point B (z=0.25, c=0.85), Point C (z=0.1, c=0.6), Point D (z=0.075, 0.5), Point E (z=0.05, c=0.2), and Point F (z=0.05, c=0.1) or located on the lines in the z-c plane. Therefore, the piezoelectric ceramic composition can be fired at a low temperature and is effective in achieving a large piezoelectric constant, a high Curie point and a small dielectric constant. A piezoelectric actuator contains the piezoelectric ceramic composition.Type: GrantFiled: June 22, 2007Date of Patent: September 29, 2009Inventors: Atsushi Yamamoto, Koji Ogiso, Koichi Hayashi