Patents by Inventor Koji Onodera

Koji Onodera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7977198
    Abstract: A semiconductor device is provided. The semiconductor device in which a field effect transistor utilizing a heterojunction is formed in a device formation region sectioned by a device separation region of a substrate comprising a semiconductor layer laminated while including a semiconductor layer having a heterojunction on a semiconductor substrate. The device separation region is composed of a layer in which a conductive impurity is introduced, and an electrode to which a positive voltage is to be applied is formed on the device separation region, specifically on the surface of at least a part of the device separation region in the periphery of the field effect transistor.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: July 12, 2011
    Assignee: Sony Corporation
    Inventors: Koji Onodera, Mitsuhiro Nakamura, Tomoya Nishida
  • Publication number: 20090280634
    Abstract: A semiconductor device is provided. The semiconductor device in which a field effect transistor utilizing a heterojunction is formed in a device formation region sectioned by a device separation region of a substrate comprising a semiconductor layer laminated while including a semiconductor layer having a heterojunction on a semiconductor substrate. The device separation region is composed of a layer in which a conductive impurity is introduced, and an electrode to which a positive voltage is to be applied is formed on the device separation region, specifically on the surface of at least a part of the device separation region in the periphery of the field effect transistor.
    Type: Application
    Filed: July 20, 2009
    Publication date: November 12, 2009
    Applicant: SONY CORPORATION
    Inventors: Koji Onodera, Mitsuhiro Nakamura, Tomoya Nishida
  • Patent number: 7579634
    Abstract: A semiconductor device is provided. The semiconductor device in which a field effect transistor utilizing a heterojunction is formed in a device formation region sectioned by a device separation region of a substrate comprising a semiconductor layer laminated while including a semiconductor layer having a heterojunction on a semiconductor substrate. The device separation region is composed of a layer in which a conductive impurity is introduced, and an electrode to which a positive voltage is to be applied is formed on the device separation region, specifically on the surface of at least a part of the device separation region in the periphery of the field effect transistor.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: August 25, 2009
    Assignee: Sony Corporation
    Inventors: Koji Onodera, Mitsuhiro Nakamura, Tomoya Nishida
  • Publication number: 20060157734
    Abstract: A semiconductor device is provided. The semiconductor device in which a field effect transistor utilizing a heterojunction is formed in a device formation region sectioned by a device separation region of a substrate comprising a semiconductor layer laminated while including a semiconductor layer having a heterojunction on a semiconductor substrate. The device separation region is composed of a layer in which a conductive impurity is introduced, and an electrode to which a positive voltage is to be applied is formed on the device separation region, specifically on the surface of at least a part of the device separation region in the periphery of the field effect transistor.
    Type: Application
    Filed: January 12, 2006
    Publication date: July 20, 2006
    Inventors: Koji Onodera, Mitsuhiro Nakamura, Tomoya Nishida
  • Publication number: 20050212049
    Abstract: A semiconductor device able to improve surge discharge capacity of a protection element (diodes in different direction each other) without changing parameter of a transistor and increasing cost drastically, having a transistor and a protection element at separated regions of semiconductor layers formed on a semiconductor substrate, which the semiconductor layers includes: a barrier layer of nondoped semiconductor formed on its surface with a gate electrode of the transistor; a first conductive type semiconductor region formed in a single or several semiconductor layers including the barrier layer as a topmost layer in a protection element side; and two second conductive type semiconductor regions formed at separated two regions in the barrier layer where the first conductive type semiconductor region is formed, which are formed with protection diodes of different direction each other at contacting surfaces with the first conductive type semiconductor region.
    Type: Application
    Filed: March 14, 2005
    Publication date: September 29, 2005
    Inventor: Koji Onodera