Patents by Inventor Koji Sadamatsu

Koji Sadamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11682723
    Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce the breakdown voltage of the terminal part. In the SiC-MOSFET with the built-in Schottky diode, a source electrode forming non-ohmic connection such as Schottky connection with the second well region is provided on the second well region formed below a gate pad in the terminal part. By the absence of ohmic connection between the second well region and the source electrode, reduction in breakdown voltage is suppressed at the terminal part.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: June 20, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hideyuki Hatta, Shiro Hino, Koji Sadamatsu, Yuichi Nagahisa
  • Patent number: 11646369
    Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce a breakdown voltage. In the SiC-MOSFET with the built-in Schottky diode, a conductive layer in Schottky connection with the second well region is provided on the second well region in the terminal part, and the conductive layer is electrically connected with a source electrode of the MOSFET. A conductive layer contact hole is provided for connecting only the conductive layer and the source electrode.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: May 9, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuichi Nagahisa, Shiro Hino, Koji Sadamatsu, Hideyuki Hatta, Kotaro Kawahara
  • Publication number: 20230036221
    Abstract: The fabrication method for a silicon carbide semiconductor device according to this disclosure includes a step of forming a dielectric film over part of a silicon carbide layer, a step of forming an ohmic electrode adjoining the dielectric film on the silicon carbide layer, a step of removing an oxidized layer on the ohmic electrode, a step of forming a mask with its opening on the side opposite to the side where the ohmic electrode is adjoining the dielectric film on the ohmic electrode having the oxidized layer removed and on the dielectric film, and a step of wet etching of a film to be etched with hydrofluoric acid with the mask formed. With the fabrication method for a silicon carbide semiconductor device described in this disclosure, it is possible to fabricate a silicon carbide semiconductor device with reduced failure.
    Type: Application
    Filed: February 13, 2020
    Publication date: February 2, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shiro HINO, Koji SADAMATSU
  • Patent number: 11508840
    Abstract: In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a second well region formed in a terminal portion sometimes reduces a breakdown voltage. In a SiC-MOSFET including Schottky diodes according to the present invention, the second well region formed in the terminal portion has a non-ohmic connection to a source electrode, and a field limiting layer lower in impurity concentration than the second well region is formed in a surface layer area of the second well region which is a region facing a gate electrode through a gate insulating film.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 22, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shiro Hino, Yuichi Nagahisa, Koji Sadamatsu, Hideyuki Hatta, Kotaro Kawahara
  • Publication number: 20220254906
    Abstract: An object of the present invention is to suppress the passage of bipolar current in a silicon carbide semiconductor device by reducing a voltage applied to a terminal well region during reflux operations. An SiC-MOSFET includes a plurality of first well regions, a second well region, a third well region in a surface layer of a drift layer, the first, second, and third well regions being of a second conductivity type. The third well region is provided on the side of the second well region opposite to the first well regions. A unit cell that includes the first well regions includes a unipolar diode. The SiC-MOSFET includes a source electrode connected to the unipolar diode and the ohmic electrode and not having ohmic connection with the second well region and the third well region.
    Type: Application
    Filed: September 6, 2019
    Publication date: August 11, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yuichi NAGAHISA, Shiro HINO, Koji SADAMATSU, Kotaro KAWAHARA, Hideyuki HATTA, Shingo TOMOHISA
  • Patent number: 11355627
    Abstract: In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a well region in a terminal region cannot be sufficiently reduced, which may reduce the reliability of elements. A SiC-MOSFET including Schottky diodes includes a gate electrode formed, through a second insulating film thicker than a gate insulating film in an active region, on a separation region between a first well region in the active region that is the closest to the terminal region and a second well region in the terminal region, wherein the second well region has a non-ohmic connection to a source electrode. Thus, a decrease in the reliability of elements is prevented.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: June 7, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuichi Nagahisa, Shiro Hino, Hideyuki Hatta, Koji Sadamatsu
  • Publication number: 20220045204
    Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce the breakdown voltage of the terminal part. In the SiC-MOSFET with the built-in Schottky diode, a source electrode forming non-ohmic connection such as Schottky connection with the second well region is provided on the second well region formed below a gate pad in the terminal part. By the absence of ohmic connection between the second well region and the source electrode, reduction in breakdown voltage is suppressed at the terminal part.
    Type: Application
    Filed: October 21, 2021
    Publication date: February 10, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hideyuki HATTA, Shiro HINO, Koji SADAMATSU, Yuichi NAGAHISA
  • Patent number: 11222973
    Abstract: A technique is provided for effectively suppressing a forward voltage shift due to occurrence of a stacking fault. A semiconductor device relating to the present technique includes a first well region of a second conductivity type, a second well region of the second conductivity type which is so provided as to sandwich the whole of a plurality of first well regions in a plan view and has an area larger than that of each of the first well regions, a third well region of the second conductivity type which is so provided as to sandwich the second well region in a plan view and has an area larger than that of the second well region, and a dividing region of a first conductivity type provided between the second well region and the third well region, having an upper surface which is in contact with an insulator.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: January 11, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shiro Hino, Koji Sadamatsu, Hideyuki Hatta, Yuichi Nagahisa, Kohei Ebihara
  • Patent number: 11189720
    Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce the breakdown voltage of the terminal part. In the SiC-MOSFET with the built-in Schottky diode, a source electrode forming non-ohmic connection such as Schottky connection with the second well region is provided on the second well region formed below a gate pad in the terminal part. By the absence of ohmic connection between the second well region and the source electrode, reduction in breakdown voltage is suppressed at the terminal part.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: November 30, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hideyuki Hatta, Shiro Hino, Koji Sadamatsu, Yuichi Nagahisa
  • Publication number: 20210226052
    Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce a breakdown voltage. In the SiC-MOSFET with the built-in Schottky diode, a conductive layer in Schottky connection with the second well region is provided on the second well region in the terminal part, and the conductive layer is electrically connected with a source electrode of the MOSFET. A conductive layer contact hole is provided for connecting only the conductive layer and the source electrode.
    Type: Application
    Filed: March 16, 2021
    Publication date: July 22, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yuichi NAGAHISA, Shiro HINO, Koji SADAMATSU, Hideyuki HATTA, Kotaro KAWAHARA
  • Patent number: 11049963
    Abstract: In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a well region in an edge portion of an active region cannot be sufficiently reduced, which may reduce the reliability of elements. In a SiC-MOSFET including Schottky diodes, the Schottky diodes formed in a terminal region are made higher in density in a plane direction than those formed in the active region or intervals between the Schottky diodes in the plane direction are shortened, without an ohmic connection between the well and the source in the terminal region.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: June 29, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shiro Hino, Yuichi Nagahisa, Koji Sadamatsu, Hideyuki Hatta, Kotaro Kawahara
  • Patent number: 10991822
    Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce a breakdown voltage. In the SiC-MOSFET with the built-in Schottky diode, a conductive layer in Schottky connection with the second well region is provided on the second well region in the terminal part, and the conductive layer is electrically connected with a source electrode of the MOSFET. A conductive layer contact hole is provided for connecting only the conductive layer and the source electrode.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: April 27, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuichi Nagahisa, Shiro Hino, Koji Sadamatsu, Hideyuki Hatta, Kotaro Kawahara
  • Publication number: 20200321462
    Abstract: In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a second well region formed in a terminal portion sometimes reduces a breakdown voltage. In a SiC-MOSFET including Schottky diodes according to the present invention, the second well region formed in the terminal portion has a non-ohmic connection to a source electrode, and a field limiting layer lower in impurity concentration than the second well region is formed in a surface layer area of the second well region which is a region facing a gate electrode through a gate insulating film.
    Type: Application
    Filed: May 28, 2020
    Publication date: October 8, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shiro HINO, Yuichi NAGAHISA, Koji SADAMATSU, Hideyuki HATTA, Kotara KAWAHARA
  • Publication number: 20200312995
    Abstract: In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a well region in a terminal region cannot be sufficiently reduced, which may reduce the reliability of elements. A SiC-MOSFET including Schottky diodes includes a gate electrode formed, through a second insulating film thicker than a gate insulating film in an active region, on a separation region between a first well region in the active region that is the closest to the terminal region and a second well region in the terminal region, wherein the second well region has a non-ohmic connection to a source electrode. Thus, a decrease in the reliability of elements is prevented.
    Type: Application
    Filed: August 23, 2018
    Publication date: October 1, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yuichi NAGAHISA, Shiro HINO, Hideyuki HATTA, Koji SADAMATSU
  • Publication number: 20200295177
    Abstract: In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a well region in an edge portion of an active region cannot be sufficiently reduced, which may reduce the reliability of elements. In a SiC-MOSFET including Schottky diodes, the Schottky diodes formed in a terminal region are made higher in density in a plane direction than those formed in the active region or intervals between the Schottky diodes in the plane direction are shortened, without an ohmic connection between the well and the source in the terminal region.
    Type: Application
    Filed: December 18, 2018
    Publication date: September 17, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shiro HINO, Yuichi NAGAHISA, Koji SADAMATSU, Hideyuki HATTA, Kotaro KAWAHARA
  • Publication number: 20190371935
    Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce the breakdown voltage of the terminal part. In the SiC-MOSFET with the built-in Schottky diode, a source electrode forming non-ohmic connection such as Schottky connection with the second well region is provided on the second well region formed below a gate pad in the terminal part. By the absence of ohmic connection between the second well region and the source electrode, reduction in breakdown voltage is suppressed at the terminal part.
    Type: Application
    Filed: February 22, 2018
    Publication date: December 5, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hideyuki HATTA, Shiro HINO, Koji SADAMATSU, Yuichi NAGAHISA
  • Publication number: 20190371936
    Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce a breakdown voltage. In the SiC-MOSFET with the built-in Schottky diode, a conductive layer in Schottky connection with the second well region is provided on the second well region in the terminal part, and the conductive layer is electrically connected with a source electrode of the MOSFET. A conductive layer contact hole is provided for connecting only the conductive layer and the source electrode.
    Type: Application
    Filed: February 22, 2018
    Publication date: December 5, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yuichi NAGAHISA, Shiro HINO, Koji SADAMATSU, Hideyuki HATTA, Kotaro KAWAHARA
  • Patent number: 10475920
    Abstract: A drift layer is made of a wide bandgap semiconductor. First well regions are formed on the drift layer. A source region is formed on each of the first well regions. A gate insulating film is formed on the first well regions. A first electrode is in contact with the source regions, and has diode characteristics allowing unipolar conduction to the drift layer between the first well regions. A second well region is formed on the drift layer. A second electrode is in contact with the second well region, and separated from a gate electrode and the first electrode.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: November 12, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Koji Sadamatsu, Shiro Hino
  • Publication number: 20190181259
    Abstract: A technique is provided for effectively suppressing a forward voltage shift due to occurrence of a stacking fault. A semiconductor device relating to the present technique includes a first well region of a second conductivity type, a second well region of the second conductivity type which is so provided as to sandwich the whole of a plurality of first well regions in a plan view and has an area larger than that of each of the first well regions, a third well region of the second conductivity type which is so provided as to sandwich the second well region in a plan view and has an area larger than that of the second well region, and a dividing region of a first conductivity type provided between the second well region and the third well region, having an upper surface which is in contact with an insulator.
    Type: Application
    Filed: April 11, 2016
    Publication date: June 13, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shiro HINO, Koji SADAMATSU, Hideyuki HATTA, Yuichi NAGAHISA, Kohei EBIHARA
  • Patent number: 10128370
    Abstract: A semiconductor device capable of increasing a value of current that flows through the whole chip until a p-n diode in a unit cell close to a termination operates and reducing a size of the chip and a cost of the chip resulting from the reduced size, and including a second well region formed on both sides, as seen in plan view, of the entirety of a plurality of first well regions, a second ohmic electrode located over the second well region, a third separation region of a first conductivity type that is positioned closer to the first well regions than the second ohmic electrode in the second well region and that is formed to penetrate the second well region from a surface layer of the second well region in a depth direction, and a second Schottky electrode located on the third separation region.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: November 13, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kohei Ebihara, Shiro Hino, Koji Sadamatsu