Abstract: The present invention provides a cell disassembly unit which accurately reproduces the position of data on a time axis when ATM cells are converted into STM signals even if cell loss occurs in an ATM network. A cell loss detection circuit disassembles the ATM cells into bytes, sends them to the memory, and detects the number of lost bytes M of the ATM cells. A sequence number generation circuit generates the sequence number N, which is N=N+1 if there is no loss, and N=N+M if there is loss, in the sequence of the transmission of bytes from the cell loss detection circuit. A write address generation circuit generates a write address, and a read address generation circuit generates a read address. A selector sends either the bytes read from the memory or dummy data generated by the dummy data generation circuit to the outside as STM signals.

Abstract: The present invention provides a cell disassembly unit which accurately reproduces the position of data on a time axis when ATM cells are converted into STM signals even if cell loss occurs in an ATM network. A cell loss detection circuit disassembles the ATM cells into bytes, sends them to the memory, and detects the number of lost bytes M of the ATM cells. A sequence number generation circuit generates the sequence number N, which is N=N+1 if there is no loss, and N=N+M if there is loss, in the sequence of the transmission of bytes from the cell loss detection circuit. A write address generation circuit generates a write address, and a read address generation circuit generates a read address. A selector sends either the bytes read from the memory or dummy data generated by the dummy data generation circuit to the outside as STM signals.

Abstract: The present invention provides a cell disassembly unit which accurately reproduces the position of data on a time axis when ATM cells are converted into STM signals even if cell loss occurs in an ATM network. A cell loss detection circuit disassembles the ATM cells into bytes, sends them to the memory, and detects the number of lost bytes M of the ATM cells. A sequence number generation circuit generates the sequence number N, which is N=N+1 if there is no loss, and N=N+M if there is loss, in the sequence of the transmission of bytes from the cell loss detection circuit. A write address generation circuit generates a write address, and a read address generation circuit generates a read address. A selector sends either the bytes read from the memory or dummy data generated by the dummy data generation circuit to the outside as STM signals.

Abstract: The present invention provides a cell disassembly unit which accurately reproduces the position of data on a time axis when ATM cells are converted into STM signals even if cell loss occurs in an ATM network. A cell loss detection circuit disassembles the ATM cells into bytes, sends them to the memory, and detects the number of lost bytes M of the ATM cells. A sequence number generation circuit generates the sequence number N, which is N=N+1 if there is no loss, and N=N+M if there is loss, in the sequence of the transmission of bytes from the cell loss detection circuit. A write address generation circuit generates a write address, and a read address generation circuit generates a read address. A selector sends either the bytes read from the memory or dummy data generated by the dummy data generation circuit to the outside as STM signals.