Patents by Inventor Koji Shibasaki

Koji Shibasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240085813
    Abstract: A cleaning method of cleaning a solution treatment apparatus for applying a coating solution onto a substrate, the solution treatment apparatus including a holder holding and rotating the substrate; a coating solution supplier; and an inner cup surrounding the holder from a lateral side and having a peripheral edge side upper surface inclining down outward in a radial direction. The cleaning method includes introducing the cleaning solution to the storage chamber via the introduction hole, discharging the cleaning solution from the discharge port and making the cleaning solution flow down along the peripheral edge side upper surface of the inner cup, thereby cleaning away the coating solution adhering to the peripheral edge side upper surface. The discharging in the cleaning discharges the cleaning solution from discharge ports of the inner cup outward in the radial direction and obliquely upward.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Kenta SHIBASAKI, Hiroichi INADA, Satoshi SHIMMURA, Koji TAKAYANAGI, Kenji YADA, Shinichi SEKI, Akihiro TERAMOTO
  • Patent number: 8128731
    Abstract: A method for separating and enriching isotopes in an efficient and low-cost manner from a condensation-system (liquid or/and solid) material including two or more different isotopes by taking advantage of the sedimentation of atoms through an acceleration field by ultra-high speed rotation. The condensation-system material is placed in a sedimentation tank which is then housed in a supercentrifuge. The supercentrifuge in its rotor is rotation driven by an ultra-high speed rotation power source, and an acceleration field of energy of 100000 G to 1500000 G, i.e., about 100 to 800 m/s in terms of peripheral velocity, is applied to the above condensed (liquid or/and solid) material under such a temperature that is specified by an isotope material to be enriched. In this case, a difference in centrifugal force applied is provided between the isotopes in the condensed (liquid or/and solid) material comprising the at least two isotopes.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: March 6, 2012
    Assignees: National University Corporation Kumamoto University, Maruwa Electronic Inc.
    Inventors: Tsutomu Mashimo, Masao Ono, Xinsheng Huang, Yusuke Iguchi, Satoru Okayasu, Hiroshi Yasuoka, Koji Shibasaki, Masanori Sueyoshi
  • Publication number: 20090272265
    Abstract: This invention provides a method for separating and enriching isotopes in an efficient and low-cost manner from a condensation-system (liquid or/and solid) material comprising two or more different isotopes by taking advantage of the sedimentation of atoms through an acceleration field by ultra-high speed rotation. A condensation-system (liquid or/and solid) material (5) comprising the two or more isotopes is placed in a sedimentation tank (for example, 2) which is then housed in a supercentrifuge. The supercentrifuge in its rotor is rotation driven by an ultra-high speed rotation power source, and an acceleration field of energy of 100000 G to 1500000 G, i.e., about 100 to 800 m/s in terms of peripheral velocity, is applied to the above condensed (liquid or/and solid) material under such a temperature that is specified by an isotope material to be enriched.
    Type: Application
    Filed: April 4, 2007
    Publication date: November 5, 2009
    Applicants: NATIONAL UNIVERSITY CORPORATION KUMAMOTO UNIVERSITY, MARUWA ELECTRONIC INC.
    Inventors: Tsutomu Mashimo, Masao Ono, Xinsheng Huang, Yusuke Iguchi, Satoru Okayasu, Hiroshi Yasuoka, Koji Shibasaki, Masanori Sueyoshi
  • Patent number: 6820503
    Abstract: An object of the present invention is to achieve more high-speed rotation of a rotor to which a test object is stored, extending the duration of high-speed rotation, and temperature control of a rotor at the time of high-speed rotation. A high-speed rotation testing apparatus of the present invention comprises: a rotor having a hollow for a test object, to which a predetermined test object is stored; a spindle connected to the rotor; a torque applying device for applying a predetermined torque to the spindle, and a casing for sealing the rotor. The casing comprises a decompressing device and a holder for holding the spindle. The holder has a bushing for supporting the spindle and a bushing supporting member for supporting the bushing by inserting thereto. By forming the inner diameter of at least one of the bushing supporting member larger than the outer diameter of the bushing, the bushing supporting member supports the bushing to be rotatable.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: November 23, 2004
    Assignees: Maruwa Electronic Inc.
    Inventors: Masanori Sueyoshi, Akira Tezuka, Koji Shibasaki, Xinsheng Huang, Toyotaka Osakabe, Masao Ono, Tsutomu Mashimo
  • Patent number: 6615670
    Abstract: A high-speed rotation testing apparatus includes a spindle 11 holding a test object S at its lower end, a driving motor 20 for applying torque to the spindle 11, and a frame 30 for supporting a rotor shaft 21 of the driving motor 20 so that the shaft is arranged toward the vertical direction of the apparatus, wherein the spindle 11 is driven directly by a driving motor 20 by inserting the spindle 11 into a through-hole 21a that penetrates the center of the rotor shaft 21 and coupling the upper ends of the rotor shaft 21 and the spindle 11 together, and the through-hole 21a has an inner diameter set so as to form a clearance in which the lower end of the spindle can swing, and further, a damping mechanism 40 that restrains swing is arranged in the vicinity of the lower end of the spindle 11, which projects from the lower end of the rotor shaft 21.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: September 9, 2003
    Assignee: Maruwa Electronic Inc.
    Inventors: Koji Shibasaki, Takeshi Watabe, Shiro Shibasaki
  • Publication number: 20030062304
    Abstract: An object of the present invention is to achieve more high-speed rotation of a rotor to which a test object is stored, extending the duration of high-speed rotation, and temperature control of a rotor at the time of high-speed rotation. A high-speed rotation testing apparatus of the present invention comprises: a rotor having a hollow for a test object, to which a predetermined test object is stored; a spindle connected to the rotor; a torque applying device for applying a predetermined torque to the spindle, and a casing for sealing the rotor. The casing comprises a decompressing device and a holder for holding the spindle. The holder has a bushing for supporting the spindle and a bushing supporting member for supporting the bushing by inserting thereto. By forming the inner diameter of at least one of the bushing supporting member larger than the outer diameter of the bushing, the bushing supporting member supports the bushing to be rotatable.
    Type: Application
    Filed: September 10, 2002
    Publication date: April 3, 2003
    Applicant: Tsutomu MASHIMO
    Inventors: Masanori Sueyoshi, Akira Tezuka, Koji Shibasaki, Xinsheng Huang, Toyotaka Osakabe, Masao Ono, Tsutomu Mashimo
  • Publication number: 20030015227
    Abstract: Disclosed are a safe and small-scaled shock wave generating apparatus and effective applications of shock wave generated by the device. Provided in the shock wave generating apparatus are a columnar rotation body, a rotation shaft projected from both end faces of the rotation body towards outside in parallel to the lateral surface of the rotation body, a rotation drive unit for providing predetermined torque to the rotation body through the rotation shaft and a controller for controlling operation of the rotation drive unit. The controller has a function of controlling the operation of the rotation drive unit so that at least a part of the lateral surface of the rotation body spins at a speed higher than the sound velocity under a condition near the periphery of the rotation body.
    Type: Application
    Filed: July 3, 2002
    Publication date: January 23, 2003
    Applicant: Kazuyoshi TAKAYAMA
    Inventors: Kazuyoshi Takayama, Gopalan Jagadeesh, Koji Shibasaki, Hiroyuki Mizunaga, Shiro Shibasaki
  • Publication number: 20020112546
    Abstract: A high-speed rotation testing apparatus includes a spindle 11 holding a test object S at its lower end, a driving motor 20 for applying torque to the spindle 11, and a frame 30 for supporting a rotor shaft 21 of the driving motor 20 so that the shaft is arranged toward the vertical direction of the apparatus, wherein the spindle 11 is driven directly by a driving motor 20 by inserting the spindle 11 into a through-hole 21a that penetrates the center of the rotor shaft 21 and coupling the upper ends of the rotor shaft 21 and the spindle 11 together, and the through-hole 21a has an inner diameter set so as to form a clearance in which the lower end of the spindle can swing, and further, a damping mechanism 40 that restrains swing is arranged in the vicinity of the lower end of the spindle 11, which projects from the lower end of the rotor shaft 21.
    Type: Application
    Filed: February 7, 2002
    Publication date: August 22, 2002
    Applicant: Maruwa Electronic Inc.
    Inventors: Koji Shibasaki, Takeshi Watabe, Shiro Shibasaki
  • Patent number: 6111317
    Abstract: A first insulating film is formed on an integrated circuit chip on which an I/O pad is formed. A first opening portion is formed above the I/O pad. A conductive layer and a barrier metal layer which are electrically connected to the I/O pad through the first opening portion are stacked on the first insulating film. The conductive layer and the barrier metal layer are patterned by a single mask. A second insulating film is formed on the resultant structure. A second opening portion is formed in the second insulating film at a position different from that of the first opening portion. A solder bump or metal pad is formed on the barrier metal layer in the second opening portion. The position of the solder bump or metal pad is defined by the second opening portion.
    Type: Grant
    Filed: January 16, 1997
    Date of Patent: August 29, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Okada, Naohiko Hirano, Hiroshi Tazawa, Eiichi Hosomi, Chiaki Takubo, Kazuhide Doi, Yoichi Hiruta, Koji Shibasaki
  • Patent number: 6061466
    Abstract: Disclosed is an apparatus and method for inspecting a connection state of a lead electrode to a bump after TAB (tape automated bonding). An LSI chip is immobilized on a stage. A flexible lead is held by a holding portion and connected to a bump. Above the chip, a CCD camera is provided. The stage is controlled to move up and down by a moving control mechanism. Each of the lead/bump connection states immediately after ILB (Inner lead bonding) is taken in the form of image data and defined as a first image data. A second image data of the lead/bump connection state is taken after the bump and lead are moved to different positions by moving the stage in order to change the position of the chip by means of the moving control mechanism. Whether or not the lead is duly connected to the bump is determined by the comparison of the first and second image data.
    Type: Grant
    Filed: December 24, 1996
    Date of Patent: May 9, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chiaki Takubo, Eiichi Hosomi, Hiroshi Tazawa, Koji Shibasaki
  • Patent number: 6049130
    Abstract: A semiconductor device comprises a semiconductor chip, an Au bump formed on the semiconductor chip, and Cu lead bonded to the Au bump through a bonding part. The Cu lead has a Cu core and a plated Sn layer formed on the Cu core, and the bonding part is formed of an Au-rich Au--Cu--Sn alloy of a ternary system having a single-phase structure containing 15 at. % or less Sn and 25 at. % or less Cu.
    Type: Grant
    Filed: May 9, 1997
    Date of Patent: April 11, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiichi Hosomi, Hiroshi Tazawa, Chiaki Takubo, Koji Shibasaki
  • Patent number: 5825081
    Abstract: The present invention is characterized by providing leads not contributing to actual connection outside the corner leads to prevent the deformation of the corner leads and improve the yield of tape carriers. A device hole is made in a near-central place of an insulating resin film. Around the device hole, outer-lead holes are made. On the insulating resin film, a plurality of wiring patterns are provided and forced to project into the device hole. The plurality of wiring patterns are formed into a plurality of inner leads, of which the outermost ones are determined to be corner leads. On each corner of the device hole, an aligning mark is provided. Dummy leads are provided closer to the aligning marks. The dummy leads are made shorter than the inner leads and corner leads.
    Type: Grant
    Filed: October 11, 1996
    Date of Patent: October 20, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiichi Hosomi, Chiaki Takubo, Hiroshi Tazawa, Koji Shibasaki
  • Patent number: 5801447
    Abstract: In a flip chip mounting type semiconductor device, on a corner portion of a chip subjected to flip chip mounting, a gate region for injecting a sealing member filled between a mounted board and the chip is arranged. In this semiconductor device, a semiconductor element has a plurality of bumps formed on the peripheral portion on a major surface along each side, a plurality of pad electrodes are formed on the major surface of the circuit board, and the pad electrodes join the bumps. A resin sealing member is filled between the semiconductor element and the circuit board. A gate region through which the resin sealing member is injected is formed on a corner portion of the semiconductor element. In the gate region, no bump is formed, or bumps are arranged at intervals smaller than that in another region. For this reason, the resin uniformly enters the space between the semiconductor element and the circuit board through the gate region.
    Type: Grant
    Filed: April 24, 1996
    Date of Patent: September 1, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naohiko Hirano, Kazuhide Doi, Chiaki Takubo, Hiroshi Tazawa, Eiichi Hosomi, Yoichi Hiruta, Takashi Okada, Koji Shibasaki
  • Patent number: 5773888
    Abstract: A semiconductor device having bump electrodes, each having a structure wherein an alloy layer such as Au--Sn formed by the reaction between the Sn-plated layer on the surface of the inner lead and the bump electrode never reach the bottom surface of the passivation opening portion, is provided. The center of the passivation opening portion is displaced apart from the center of an electrode pad to a direction toward the center of the semiconductor substrate. The center of the passivation opening portion is displaced away from the outer lead and close to the tip end of the inner lead in contrast to the center of the bump electrode. By positioning the passivation opening portion such that the center thereof is located nearer to the center of semiconductor substrate than a center of the bump electrode, without changing the height of the bump electrode or the size of the passivation opening portion, the Au--Sn alloy etc.
    Type: Grant
    Filed: November 9, 1995
    Date of Patent: June 30, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiichi Hosomi, Chiaki Takubo, Hiroshi Tazawa, Koji Shibasaki
  • Patent number: 5747881
    Abstract: A semiconductor device comprises a semiconductor chip, an Au bump formed on the semiconductor chip, and Cu lead bonded to the Au bump through a bonding part. The Cu lead has a Cu core and a plated Sn layer formed on the Cu core, and the bonding part is formed of an Au--rich Au--Cu--Sn alloy of a ternary system having a single-phase structure with a composition of 15 atomic % Sn or less and 25 atomic % Cu or less.
    Type: Grant
    Filed: January 30, 1996
    Date of Patent: May 5, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiichi Hosomi, Hiroshi Tazawa, Chiaki Takubo, Koji Shibasaki
  • Patent number: 5631499
    Abstract: A semiconductor device having a bump electrode includes a first conductive layer formed on a predetermined portion of a substrate. An insulating layer is formed on the substrate and the first conductive layer. The insulating layer has an opening portion such that a predetermined portion of the first conductive layer is exposed. A second conductive layer is formed on the first conductive layer, a side wall of the opening portion of the insulating layer, and an upper surface of the insulating layer. A third conductive layer is formed to cover at least the insulating layer on the first conductive layer and the second conductive layer along the portion. A fourth conductive layer is formed on the third conductive layer to have an over hang portion. A side etch portion is formed surrounded with an over hang portion of the fourth conductive layer, the third conductive layer, and the insulating layer.
    Type: Grant
    Filed: June 3, 1996
    Date of Patent: May 20, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiichi Hosomi, Chiaki Takubo, Hiroshi Tazawa, Ryouichi Miyamoto, Takashi Arai, Koji Shibasaki
  • Patent number: 5615822
    Abstract: In this invention, a designed value of a lead width is previously input and a bonding load suitable for the designed lead width is previously input before the step of continuously bonding a TAB tape on a semiconductor chip is effected. Next, the TAB tape and chip are carried to preset positions, and after recognition of the positions of the tape and chip and the alignment of the tape and chip by use of a CCD camera are completed, the inner lead width is actually measured by use of the CCD camera. The measured lead width is compared with the designed lead width, and when a difference therebetween exceeds a preset reference value, the bonding load is changed to a bonding load suitable for the measured lead width of the lead to be actually bonded based on the ratio of the measured lead width to the designed lead width and then the bonding operation is effected by the suitable bonding load.
    Type: Grant
    Filed: September 22, 1995
    Date of Patent: April 1, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chiaki Takubo, Hiroshi Tazawa, Eiichi Hosomi, Koji Shibasaki