Abstract: Provided is a secondary battery, including: an electrode wound body having a structure in which a band-shaped positive electrode and a band-shaped negative electrode are stacked with a separator interposed therebetween and wound; and a battery can that accommodates the electrode wound body, wherein the positive electrode has a positive electrode active material layer on both sides of a band-shaped positive electrode foil, the negative electrode has a negative electrode active material layer on both sides of a band-shaped negative electrode foil, the electrode wound body has a positive electrode foil tab between a winding starting side and a winding ending side of the positive electrode and a negative electrode tab between a winding starting side and a winding ending side of the negative electrode, the positive electrode foil tab has a plate-like part joined on the winding starting side of the positive electrode, and a comb-like part protruding from the positive electrode, and the comb-like part is a connectin

Abstract: Provided is a secondary battery including an electrode wound body having a structure in which a positive electrode having a belt shape and a negative electrode having a belt shape are stacked and wound with a separator interposed between the positive electrode having a belt shape and the negative electrode having a belt shape and an exterior can housing the electrode wound body, in which the positive electrode includes positive electrode active material layers on both surfaces of a positive electrode foil having a belt shape, the positive electrode has two edges being intersections of an end surface on a winding start side and surfaces of the positive electrode active material layers in sectional view of the positive electrode, and an insulating member having a length of 10 mm or more and 40 mm or less is disposed on a surface of the separator on the winding start side of the electrode wound body at a position facing at least one of the edges of a positive electrode.

Abstract: A battery incudes wound positive and negative electrodes, where the wound positive electrode includes a positive electrode current collector, a first positive electrode active material layer provided on an inner surface of the positive electrode current collector, and a second positive electrode active material layer provided on an outer surface of the positive electrode current collector. An inner circumference side end portion and an outer circumference side end portion of the positive electrode current collector are covered with the first active material layer, and the first positive electrode active material layer includes a low area density portion in a portion facing an inner circumference side end portion of the wound positive electrode.

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

Abstract: A secondary battery includes at least: a laminated electrode body 20 in which an electrode member 21 and a separator 26 are laminated, in which a suppressing member 31A suppressing a movement of the separator 26 with respect to the electrode member 21 is disposed between a portion 21A of the electrode member 21 and a portion of the separator 26, in an uneven portion 27A existing in the laminated electrode body 20.

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

Abstract: A battery incudes wound positive and negative electrodes, where the wound positive electrode includes a positive electrode current collector, a first positive electrode active material layer provided on an inner surface of the positive electrode current collector, and a second positive electrode active material layer provided on an outer surface of the positive electrode current collector. An inner circumference side end portion and an outer circumference side end portion of the positive electrode current collector are covered with the first active material layer, and the first positive electrode active material layer includes a low area density portion in a portion facing an inner circumference side end portion of the wound positive electrode.

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

Abstract: A secondary battery includes at least: a laminated electrode body 20 in which an electrode member 21 and a separator 26 are laminated, in which a suppressing member 31A suppressing a movement of the separator 26 with respect to the electrode member 21 is disposed between a portion 21A of the electrode member 21 and a portion of the separator 26, in an uneven portion 27A existing in the laminated electrode body 20.

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

Abstract: There is provided a highly secure cryptographic processing apparatus and method where an analysis difficulty is increased. In a Feistel type common key block encrypting process in which an SPN type F function having a nonlinear conversion section and a linear conversion section is repeatedly executed a plurality of rounds. The linear conversion process of an F function corresponding to each of the plurality of rounds is performed as a linear conversion process which employs an MDS (Maximum Distance Separable) matrix, and a linear conversion process is carried out which employs a different MDS matrix at least at each of consecutive odd number rounds and consecutive even number rounds. This structure makes it possible to increase the minimum number (a robustness index against a differential attack in common key block encryption) of the active S box in the entire encrypting function.

Abstract: A semiconductor intergrated circuit including p-type active regions and n-type active regions provided on a semiconductor substrate. Gate interconnect lines are arranged in a first predetermined direction on the p-type active regions and the n-type active regions. One of the p-type active regions and the n-type regions is provided with at least one protruding part for holding contact holes. A width along a second predetermined direction of the protruding part is larger than a width along the second direction of a space defined between two adjacent gate interconnect lines on the p-type active regions and the n-type active regions.

Abstract: P-type active regions (1) and n-type active regions (2) are provided on a semiconductor substrate (not shown). Three gate interconnect lines (3, 4, 5) are arranged on the p-type active regions (1) and the n-type active regions (2). The p-type active regions (1) are provided with protruding parts for holding therein contact holes (6, 7). The contact holes (6, 7) are each arranged on the side opposite to that facing the n-type active regions (2) (in FIG. 1, on the upper part of the p-type active region (1)). The contact hole (6) in one protruding part is provided between the gate interconnect lines (3) and (4). The contact hole (7) in other protruding part is formed between the gate interconnect lines (4) and (5).

Abstract: A layout pattern of a memory cell circuit has a plurality of basic cells. Each basic cell has a small aspect ratio. Each basic cell has a NMOS transistor and a PMOS transistor. In the layout pattern, one basic cell is arranged in each row direction and the sixteen basic cells are arranged in each column direction.

Abstract: A semiconductor memory in which integration is enhanced is provided. An NMOS transistor Qn1 has a gate connected to a write word line WWLn, a source connected to a write bit line WBLn, and a drain connected to a node N1. An NMOS transistor Qn2 has a gate connected to a read word line RWLn and a source connected to a read bit line RBLn. An NMOS transistor Qn3 has a gate connected to the drain of the NMOS transistor Qn1, a source connected to a ground level, and a drain connected to the drain of the NMOS transistor Qn2. An NMOS transistor Qn4 has a gate connected to a ground level, a source connected to the source of the NMOS transistor Qn3, and a drain connected to the drain of the NMOS transistor Qn1. The NMOS transistor Qn4 is kept off so that the drain of the NMOS transistor Qn1 is dielectrically isolated from the source of the NMOS transistor Qn3.

Abstract: When stored data of a plurality of memory cells (MC00 to MC03, MC10 to MC13, MC20 to MC23, MC30 to MC33) arranged in a matrix are sequentially read out, a reading access control circuit (101) outputs a row address and a column address to a row decoder (102) and a reading bit-line selector (103), respectively, for an access to the memory cells. The reading access control circuit (101) outputs the row address and the column address so that an n-type memory cell may be first selected by the reading bit-line selector (103) after activation of the selected reading word line every time one of the reading word lines (RWL0 to RWL3) is selected by the row decoder (102). With this configuration, data can be sequentially read out at higher speed from a plurality of memory cells arranged in a matrix.