Abstract: A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region.

Abstract: A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor.

Abstract: The conventional A/D converter has a drawback that the conversion precision is degraded when the operation periods of the constituents of the A/D converter are shortened due to the duty ratio of an external input clock because the operation periods of the constituents of the A/D converter depend on the pulse width of the external input clock. However, a highly-precise A/D conversion operation independent of the duty ratio of the external input clock can be realized by providing a circuit for detecting the operation periods of the constituents of the A/D converter, and adjusting the duty ratio of the operation clock according to the detected operation periods of the constituents of the A/D converter.

Abstract: A comparator used in a parallel-type A/D converter, wherein a comparator 100 includes reset transistors mra and mrb. When the comparator 100 is in the Reset state, the inverted signal /CLK of the clock signal is given to the PMOS reset transistors mra and mrb so as to forcibly reset both of the voltages at two internal nodes Va and Vb being a differential pair to a predetermined reset voltage by the reset transistors mra and mrb. The inverted signal /CLK of the clock signal is produced with a predetermined delay. Thus, when the comparator 100 is in the Reset state, the point in time at which to cancel the reset of the internal nodes Va and Vb is delayed from that at which the comparator performs a comparison operation. Therefore, even if the frequency of the clock signal and the frequency of the analog input signal are high, the voltages at the internal nodes forming a differential pair are well-balanced when the comparator is in the Reset state, thus improving the voltage comparison precision.

Abstract: A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region.

Abstract: The conventional A/D converter has a drawback that the conversion precision is degraded when the operation periods of the constituents of the A/D converter are shortened due to the duty ratio of an external input clock because the operation periods of the constituents of the A/D converter depend on the pulse width of the external input clock. However, a highly-precise A/D conversion operation independent of the duty ratio of the external input clock can be realized by providing a circuit for detecting the operation periods of the constituents of the A/D converter, and adjusting the duty ratio of the operation clock according to the detected operation periods of the constituents of the A/D converter.

Abstract: A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor.

Abstract: In a pipeline type A/D converter apparatus including A/D converter circuit parts connected in cascade with each other and A/D converting a sample hold signal in a pipeline form, each A/D converter circuit part includes a pre-A/D converter circuit for A/D converting an input signal into a digital signal, and a multiplying D/A converter circuit for D/A converting the digital signal into an analog control signal, and D/A converting the input signal by sampling, holding and amplifying the input signal using a sampling capacitor based on the analog control signal. A precharge circuit precharges a sampling capacitor before sampling so as to attain a predetermined output value in accordance with a digital input to output characteristic substantially adapted to an input to output characteristic of each A/D converter circuit part that presents an output signal corresponding to the input signal to each A/D converter circuit part.

Abstract: A comparator used in a parallel-type A/D converter, wherein a comparator 100 includes reset transistors mra and mrb. When the comparator 100 is in the Reset state, the inverted signal /CLK of the clock signal is given to the PMOS reset transistors mra and mrb so as to forcibly reset both of the voltages at two internal nodes Va and Vb being a differential pair to a predetermined reset voltage by the reset transistors mra and mrb. The inverted signal /CLK of the clock signal is produced with a predetermined delay. Thus, when the comparator 100 is in the Reset state, the point in time at which to cancel the reset of the internal nodes Va and Vb is delayed from that at which the comparator performs a comparison operation. Therefore, even if the frequency of the clock signal and the frequency of the analog input signal are high, the voltages at the internal nodes forming a differential pair are well-balanced when the comparator is in the Reset state, thus improving the voltage comparison precision.

Abstract: In a pipeline type A/D converter apparatus including A/D converter circuit parts connected in cascade with each other and A/D converting a sample hold signal in a pipeline form, each A/D converter circuit part includes a pre-A/D converter circuit for A/D converting an input signal into a digital signal, and a multiplying D/A converter circuit for D/A converting the digital signal into an analog control signal, and D/A converting the input signal by sampling, holding and amplifying the input signal using a sampling capacitor based on the analog control signal. A precharge circuit precharges a sampling capacitor before sampling so as to attain a predetermined output value in accordance with a digital input to output characteristic substantially adapted to an input to output characteristic of each A/D converter circuit part that presents an output signal corresponding to the input signal to each A/D converter circuit part.

Abstract: In an A/D converter, each preamp 102 includes a preamp gain adjusting circuit 109. The preamp gain adjusting circuit 109 suppresses the gain of the preamp 102 and restricts a positive-negative output potential difference of the preamp only when the positive-negative output potential difference of the preamp 102 exceeds a reference potential. Accordingly, in the case where the frequency of an input signal to the A/D converter is high, even when the gain of the preamp is increased due to fabrication process variation, temperature variation or supply voltage variation, output strain of the preamp is minimally caused, and the characteristic degradation of the A/D converter can be suppressed.

Abstract: In an A/D converter, each preamp 102 includes a preamp gain adjusting circuit 109. The preamp gain adjusting circuit 109 suppresses the gain of the preamp 102 and restricts a positive-negative output potential difference of the preamp only when the positive-negative output potential difference of the preamp 102 exceeds a reference potential. Accordingly, in the case where the frequency of an input signal to the A/D converter is high, even when the gain of the preamp is increased due to fabrication process variation, temperature variation or supply voltage variation, output strain of the preamp is minimally caused, and the characteristic degradation of the A/D converter can be suppressed.

Abstract: In a flash A/D converter including a plurality of differential amplifier circuits and a plurality of voltage comparator circuits, a regulator circuit is provided. The regulator circuit automatically regulates a bias voltage of each of the plurality of differential amplifier circuits in a differential amplifier circuit array to make an output dynamic range for the differential amplifier circuits match an input dynamic range for the plurality of voltage comparator circuits. Therefore, even if the input dynamic range for the voltage comparator circuits is narrowed with reduction in a power supply voltage, the output dynamic range for the differential amplifier circuits and the input dynamic range for the voltage comparator circuits match, thus resulting in a high A/D conversion accuracy.

Abstract: In a flash A/D converter including a plurality of differential amplifier circuits and a plurality of voltage comparator circuits, a regulator circuit is provided. The regulator circuit automatically regulates a bias voltage of each of the plurality of differential amplifier circuits in a differential amplifier circuit array to make an output dynamic range for the differential amplifier circuits match an input dynamic range for the plurality of voltage comparator circuits. Therefore, even if the input dynamic range for the voltage comparator circuits is narrowed with reduction in a power supply voltage, the output dynamic range for the differential amplifier circuits and the input dynamic range for the voltage comparator circuits match, thus resulting in a high A/D conversion accuracy.

Abstract: An A/D converter of the present invention includes: a reference voltage generation section for generating a plurality of reference voltages; a differential amplification section for amplifying a voltage difference between each of the plurality of reference voltages and an input signal voltage so as to generate a plurality of output voltage sets, each of the plurality of output voltage sets including complementary non-inverted and inverted output voltages; and an operating section for receiving the plurality of output voltage sets, the operating section being operated according to a clock signal.

Abstract: An A/D converter of the present invention includes: a reference voltage generation section for generating a plurality of reference voltages; a differential amplification section for amplifying a voltage difference between each of the plurality of reference voltages and an input signal voltage so as to generate a plurality of output voltage sets, each of the plurality of output voltage sets including complementary non-inverted and inverted output voltages; and an operating section for receiving the plurality of output voltage sets, the operating section being operated according to a clock signal.

Abstract: In a write driver circuit for switching the direction of a write current passing through a magnetic head or the like having an inductance component, an H-shaped bridge circuit is formed by using four NPN transistors in order to switch the write current at a high speed. Four switching means for controlling the base potentials of the four NPN transistors are provided and two switching means for rapidly decreasing the base potential of one of the two NPN transistors on the power source side, which is turned off when the write current passing through the magnetic head is switched are provided, thereby widening a voltage difference occurring between both terminals of the magnetic head.

Abstract: A magnetic recording device includes a magnetic disk drive for recording desired information as a magnetic signal and a reproducing signal amplifier for amplifying a small electric signal obtained by converting the magnetic signal. The reproducing signal amplifier includes an amplifier for amplifying a small electric signal supplied through an input terminal into an amplified signal having an appropriate amplitude, a central value detection circuit for detecting a central value of the AC component of the amplified signal output by the amplifier and outputting a central value signal consisting of the DC component of the amplified signal, and a subtracter for obtaining a difference between the amplified signal and the central value signal and outputting a reproducing signal.

Abstract: An amplifier circuit for amplifying a change in a resistance value of a magnetic resistance element is formed by connecting a first and a second current mirror circuits having the same structure in cascode, so that a voltage change is amplified without using a capacitive coupling. Hence, a high-pass filter is not created as a parasitic circuit, whereby a gain is maintained high in the low frequency region and a low frequency characteristic is excellent. Further, since control electrodes of transistors which form each current mirror circuit are grounded through the capacitance, a noise is reduced without using a conventional feedback circuit. This eliminates an influence of the feedback circuit over a high frequency characteristic, and therefore, a high frequency characteristic becomes excellent.