Patents by Inventor Koji Takaya
Koji Takaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10567687Abstract: The present disclosure relates to a solid-state imaging device and an electronic apparatus which can accurately extract a noise component so as to appropriately remove the noise component caused by stray light.Type: GrantFiled: September 30, 2016Date of Patent: February 18, 2020Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Koji Takaya, Ryoji Suzuki
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Publication number: 20180220092Abstract: The present disclosure relates to a solid-state imaging device and an electronic apparatus which can accurately extract a noise component so as to appropriately remove the noise component caused by stray light.Type: ApplicationFiled: September 30, 2016Publication date: August 2, 2018Applicant: Sony CorporationInventors: KOJI TAKAYA, RYOJI SUZUKI
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Patent number: 7804127Abstract: A semiconductor non-volatile memory cell includes an Si (silicon) layer containing substrate including an activation region having a ridge portion; an element separation region embedded in both sides of the activation region; a gate electrode with a gate insulation film inbetween formed over the ridge portion for covering a part of both side surfaces of the ridge portion and an upper surface of the element separation region; a channel forming region formed in a surface layer region of the ridge portion; an extension region formed on both sides of the channel forming region in the longitudinal direction; and an electric charge accumulation layer capable of accumulating electric charges and a sidewall formed on the extension region and one or both of side surfaces of the gate electrode facing with each other in the longitudinal direction.Type: GrantFiled: June 12, 2008Date of Patent: September 28, 2010Assignee: Oki Electric Industry Co., Ltd.Inventors: Koji Takaya, Akiyuki Minami
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Patent number: 7601594Abstract: A method for fabricating a semiconductor memory, the method including: forming an element isolation region in a concave portion of the semiconductor substrate; forming a layer of a gate electrode material so as to cover the concave portion and the element isolation region; forming a gate electrode by forming a mask on a surface of the layer of a gate electrode material so that a height from an upper surface of the convex portion to the surface of the mask is higher than a height from the surface of the element isolation region to the upper surface of the convex portion and by patterning the layer of the gate electrode material; forming a charge storing layer at least one of side surfaces of the gate electrode in contact with the convex portion; and forming a sidewall on a part of the charge storing layer.Type: GrantFiled: March 11, 2008Date of Patent: October 13, 2009Assignee: Oki Semiconductor Co., Ltd.Inventor: Koji Takaya
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Publication number: 20090045454Abstract: A semiconductor non-volatile memory cell includes an Si (silicon) layer containing substrate including an activation region having a ridge portion; an element separation region embedded in both sides of the activation region; a gate electrode with a gate insulation film inbetween formed over the ridge portion for covering a part of both side surfaces of the ridge portion and an upper surface of the element separation region; a channel forming region formed in a surface layer region of the ridge portion; an extension region formed on both sides of the channel forming region in the longitudinal direction; and an electric charge accumulation layer capable of accumulating electric charges and a sidewall formed on the extension region and one or both of side surfaces of the gate electrode facing with each other in the longitudinal direction.Type: ApplicationFiled: June 12, 2008Publication date: February 19, 2009Inventors: Koji Takaya, Akiyuki Minami
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Publication number: 20080254585Abstract: A method for fabricating a semiconductor memory, the method including: forming an element isolation region in a concave portion of the semiconductor substrate; forming a layer of a gate electrode material so as to cover the concave portion and the element isolation region; forming a gate electrode by forming a mask on a surface of the layer of a gate electrode material so that a height from an upper surface of the convex portion to the surface of the mask is higher than a height from the surface of the element isolation region to the upper surface of the convex portion and by patterning the layer of the gate electrode material; forming a charge storing layer at least one of side surfaces of the gate electrode in contact with the convex portion; and forming a sidewall on a part of the charge storing layer.Type: ApplicationFiled: March 11, 2008Publication date: October 16, 2008Applicant: OKI ELECTRIC INDUSTRY CO., LTD.Inventor: Koji Takaya
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Publication number: 20080197404Abstract: A semiconductor memory device is fabricated by: forming a device isolation region in a recessed portion of a semiconductor substrate having an irregularly-shaped portion; forming a gate electrode wiring trench in a direction orthogonal to a longitudinal direction of an active region which is a projecting portion of the semiconductor substrate having the irregularly-shaped portion in the device isolation region; forming a gate electrode material layer so as to fill the gate electrode wiring trench; forming a gate electrode by patterning the layer formed of the gate electrode material; forming an active region by etching the device isolation region; forming a charge storage layer on at least one side surface of the gate electrode, the surface being adjacent to the projecting portion of the semiconductor substrate having the irregularly-shaped portion; and forming a side wall on at least a part of the charge storage layer.Type: ApplicationFiled: December 21, 2007Publication date: August 21, 2008Applicant: OKI ELECTRIC INDUSTRY CO., LTD.Inventor: Koji Takaya
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Publication number: 20080116508Abstract: A semiconductor memory device of the invention includes a substrate, a convex semiconductor formed convexly on the substrate, a channel region formed within the convex semiconductor, source and drain regions formed within the convex semiconductor so as to sandwich the channel region, a resistance transition region formed so as to be sandwiched at least between the channel region and the source region or between the channel region and the drain region within the convex semiconductor, a gate electrode covering at least both side-faces of a part where the channel region of the convex semiconductor is formed and charge trapping layers covering at least both side-faces of a part of the convex semiconductor where the resistance transition regions are formed. Due to this configuration, there is provided the semiconductor memory device that can prevent its erroneous operation.Type: ApplicationFiled: November 2, 2007Publication date: May 22, 2008Applicant: OKI ELECTRIC INDUSTRY CO., LTD.Inventors: Takahisa HAYASHI, Shinya OZAWA, Koji TAKAYA
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Patent number: 7371635Abstract: A method of manufacturing a semiconductor device includes: forming a transistor with first and second ends of a main current path, and a control electrode, covering the transistor with a first insulating film, forming first through third openings that expose the first and second ends and the control electrode, and burying or filling first to third conductive materials in the first to third openings respectively, forming the ferroelectric capacitor by laminating the first electrode, the ferroelectric film, and the second electrode, laminating the second insulating film and the moisture diffusion protective film, forming the fourth opening to expose the third conductive material through the second insulating film and the moisture diffusion protective film, and forming a first wiring layer, which has electrical connection with the control electrode.Type: GrantFiled: July 23, 2004Date of Patent: May 13, 2008Assignee: Oki Electric Industry Co., Ltd.Inventor: Koji Takaya
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Patent number: 7273760Abstract: The present invention provides a method of manufacturing a semiconductor device that can inhibit deterioration of the ferroelectric film cased by hydrogen generated in a wiring layer. The method of manufacturing a semiconductor device includes steps of forming the ferroelectric capacitor by laminating first electrode 8, ferroelectric film 9, second electrode 10, covering the ferroelectric capacitor by insulating film 11, forming opening 13d that exposes the second electrode 10 on the insulating film 11, depositing or forming conductive hydrogen protective film 20, forming wiring layer 14 on the conductive hydrogen protective film 20, and patterning the wiring layer 14 and the conductive hydrogen protective layer 20 after forming the wiring layer 14.Type: GrantFiled: July 23, 2004Date of Patent: September 25, 2007Assignee: Oki Electric Industry Co., Ltd.Inventor: Koji Takaya
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Publication number: 20070010066Abstract: A method for manufacturing a semiconductor device is disclosed, which comprises the steps of (i) forming a circuit element on a semiconductor substrate, (ii) forming a dielectric that covers the circuit element, (iii) forming a first electrode on the dielectric, (iv) forming a ferroelectric film on the first electrode, (v) forming a second electrode on the ferroelectric film, (vi) forming a hardmask on the second electrode, (vii) etching the first electrode, the ferroelectric film, and the second electrode using the hardmask as an etching mask, and (viii) removing the hardmask and redeposition that is attached after said etching to a sidewall of the ferroelectric film simultaneously.Type: ApplicationFiled: June 22, 2006Publication date: January 11, 2007Applicant: OKI ELECTRIC INDUSTRY CO., LTD.Inventor: Koji Takaya
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Publication number: 20050145985Abstract: The present invention provides a method of manufacturing a semiconductor device that can inhibit deterioration of the ferroelectric film cased by hydrogen generated in a wiring layer. The method of manufacturing a semiconductor device includes steps of forming the ferroelectric capacitor by laminating first electrode 8, ferroelectric film 9, second electrode 10, covering the ferroelectric capacitor by insulating film 11, forming opening 13d that exposes the second electrode 10 on the insulating film 11, depositing or forming conductive hydrogen protective film 20, forming wiring layer 14 on the conductive hydrogen protective film 20, and patterning the wiring layer 14 and the conductive hydrogen protective layer 20 after forming the wiring layer 14.Type: ApplicationFiled: July 23, 2004Publication date: July 7, 2005Applicant: Oki Electric Co., Ltd.Inventor: Koji Takaya
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Publication number: 20050139881Abstract: A method of manufacturing a semiconductor device includes: forming a transistor with first and second ends 3a and 3b of a main current path, and a control electrode 5, covering the transistor with a first insulating film 6, forming first through third openings that expose the first and second ends 3a and 3b and the control electrode 5, and burying or filling first to third conductive materials 7a-7c in the first to third openings respectively, forming the ferroelectric capacitor by laminating the first electrode 8, the ferroelectric film 9, and the second electrode 10, laminating the second insulating film 11 and the moisture diffusion protective film 12, forming the fourth opening 13c to expose the third conductive material 7c through the second insulating film 11 and the moisture diffusion protective film 12, and forming a first wiring layer 14c, which has electrical connection with the control electrode 5.Type: ApplicationFiled: July 23, 2004Publication date: June 30, 2005Applicant: Oki Electric Co., Ltd.Inventor: Koji Takaya