Patents by Inventor Koji Ueta

Koji Ueta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7892886
    Abstract: At least a part of an outer edge of a surface where a circuit forming region, for example, of a semiconductor substrate that forms a semiconductor chip is arranged (a region surrounded by a scribe line around the circuit forming region) is cut or polished, so as to form a smooth slope is chamfered non-parallel and non-vertical to the circuit forming region. Then, a code indicating management information is assigned to the slope. Further, a plurality of semiconductor chips are stacked to manufacture a semiconductor device.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: February 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Koji Ueta
  • Publication number: 20090289331
    Abstract: At least a part of an outer edge of a surface where a circuit forming region, for example, of a semiconductor substrate that forms a semiconductor chip is arranged (a region surrounded by a scribe line around the circuit forming region) is cut or polished, so as to form a smooth slope is chamfered non-parallel and non-vertical to the circuit forming region. Then, a code indicating management information is assigned to the slope. Further, a plurality of semiconductor chips are stacked to manufacture a semiconductor device.
    Type: Application
    Filed: April 22, 2009
    Publication date: November 26, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Koji Ueta