Abstract: When a scene group including plural scenes, for example a group of scenes bookmarked during viewing of video contents is inputted, a combination of a scene and metadata in a group of metadata that represents characteristics of the scene, corresponding to the respective scenes in the scene group, which combination has a largest distance between the metadata, is selected as explanatory descriptions that are explanations for distinguishing among the scenes, and the selected explanatory descriptions for each scene included in the scene group is added to each scene.

Abstract: A program structuring device includes a play-list collecting unit that collects a play list for a content in which a time series is defined; a first storage unit that stores cutoff points that appear in the play list and are breakpoints of a program structure of the content, in correspondence with a frequency of appearance of each of the cutoff points; a calculating unit that calculates a level of relevance between scene segments defined by the cutoff points from the frequency of appearance of each of the cutoff points; an extracting unit that extracts multi-level chapter divisions based on the level of relevance; and a second storage unit that stores the extracted multi-level chapter divisions structured into a tree form.

Abstract: An information retrieval system, includes speech recognition means for making speech recognition for a spoken question to generate first text information, generation means for modifying the first text information to generate second text information as a interrogative to make a search for an answer to the question, and search means for searching the answer from a document database by using the second text information.

Abstract: A semiconductor integrated circuit includes a random access memory; a memory BIST circuit that writes a memory test pattern into the random access memory after the random access memory passes a failure test; a scan chain which effects shift-in of a logic test pattern generated by automatic pattern generation on condition that the memory test pattern is read without being rewritten; and a combinational logic circuit that can configure a system logic circuit along with the scan chain. The random access memory outputs a data signal read from the memory test pattern, by a read command signal that is attributable to the logic test pattern and is passed the combinational logic circuit. The test result that is attributed to the read data signal and is passed through the combinational logic circuit is input to the scan chain. The scan chain shifts out the test result.

Abstract: When a scene group including plural scenes, for example a group of scenes bookmarked during viewing of video contents is inputted, a combination of a scene and metadata in a group of metadata that represents characteristics of the scene, corresponding to the respective scenes in the scene group, which combination has a largest distance between the metadata, is selected as explanatory descriptions that are explanations for distinguishing among the scenes, and the selected explanatory descriptions for each scene included in the scene group is added to each scene.

Abstract: A program structuring device includes a play-list collecting unit that collects a play list for a content in which a time series is defined; a first storage unit that stores cutoff points that appear in the play list and are breakpoints of a program structure of the content, in correspondence with a frequency of appearance of each of the cutoff points; a calculating unit that calculates a level of relevance between scene segments defined by the cutoff points from the frequency of appearance of each of the cutoff points; an extracting unit that extracts multi-level chapter divisions based on the level of relevance; and a second storage unit that stores the extracted multi-level chapter divisions structured into a tree form.

Abstract: A semiconductor integrated circuit includes a random access memory; a memory BIST circuit that writes a memory test pattern into the random access memory after the random access memory passes a failure test; a scan chain which effects shift-in of a logic test pattern generated by automatic pattern generation on condition that the memory test pattern is read without being rewritten; and a combinational logic circuit that can configure a system logic circuit along with the scan chain. The random access memory outputs a data signal read from the memory test pattern, by a read command signal that is attributable to the logic test pattern and is passed the combinational logic circuit. The test result that is attributed to the read data signal and is passed through the combinational logic circuit is input to the scan chain. The scan chain shifts out the test result.

Abstract: A method for generating a test vector of an IC including: designating a retrieval condition to select a path on which a signal can be transmitted in the circuit; executing a timing analysis of the circuit based on a circuit information of the circuit, retrieving the path satisfying the retrieval condition, and generating a path list in which cells composing the retrieved path are put in order of executing the timing analysis; generating a test vector to test a path delay fault of the circuit based on the path list; designating an ending condition to end generation of the test vector when the path in the path list for the test vector is distributed over the circuit; and stopping generation of the path list when the ending condition is satisfied.

Abstract: An information retrieval system, includes speech recognition means for making speech recognition for a spoken question to generate first text information, generation means for modifying the first text information to generate second text information as a interrogative to make a search for an answer to the question, and search means for searching the answer from a document database by using the second text information.

Abstract: A method for generating a test vector of a semiconductor integrated circuit including: designating a retrieval condition to select a path on which a signal can be transmitted in the circuit; executing a timing analysis of the circuit based on a circuit information of the circuit, retrieving the path satisfying the retrieval condition, and generating a path list in which cells composing the retrieved path are put in order of executing the timing analysis; generating a test vector to test a path delay fault of the circuit based on the path list; designating an ending condition to end generation of the test vector when the path in the path list for the test vector is distributed over the circuit; and stopping generation of the path list when the ending condition is satisfied.