Abstract: A multiport memory device includes first and second memory cell arrays divided by a shared sense amplifier circuit, a first serial data register capable of transferring data with a row in the first memory array through a first data bus, a second serial data register capable of transferring data with a row in the second memory array through a second data bus. The multiport memory device activates both the first and second data bus for transferring data of a row in the first or second memory array both to the first and second serial data registers in the same data transfer cycle in response to a dual read transfer instructions.