Patents by Inventor Koji Usuda

Koji Usuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050009282
    Abstract: A semiconductor apparatus includes a substrate, a buffer layer made of a monocrystal semiconductor material and formed on the substrate, a strained-Si layer formed on the buffer layer and having a lattice constant different from that of the buffer layer, a monocrystal insulating film formed on the strained-Si layer and made of a material having a rare earth structure with a lattice constant different from that of Si, and an electrode formed on the insulating film.
    Type: Application
    Filed: August 9, 2004
    Publication date: January 13, 2005
    Inventors: Koji Usuda, Shinichi Takagi
  • Publication number: 20040126958
    Abstract: A semiconductor device comprises a base substrate, an insulating film formed on the substrate, an undoped first and lattice-relaxed semiconductor layer formed on the insulating film, a second semiconductor layer having a tensile strain and formed on the first semiconductor layer, and a MISFET formed on the second semiconductor layer. Since the MISFET is formed in a strained Si layer, electrons are prevented from scattering in a channel region, improving the electron mobility. Furthermore, since the MISFET is formed in a thin SOI layer having a thickness of 100 nm or less, it is possible to reduce a parasitic capacitance in addition to the improvement of the electron mobility. As a result, the MISFET excellent in drivability can be obtained.
    Type: Application
    Filed: December 17, 2003
    Publication date: July 1, 2004
    Inventors: Koji Usuda, Shinichi Takagi
  • Publication number: 20040094758
    Abstract: A semiconductor apparatus includes a substrate, a buffer layer made of a monocrystal semiconductor material and formed on the substrate, a strained-Si layer formed on the buffer layer and having a lattice constant different from that of the buffer layer, a monocrystal insulating film formed on the strained-Si layer and made of a material having a rare earth structure with a lattice constant different from that of Si, and an electrode formed on the insulating film.
    Type: Application
    Filed: July 28, 2003
    Publication date: May 20, 2004
    Inventors: Koji Usuda, Shinichi Takagi
  • Patent number: 6690043
    Abstract: A semiconductor device comprises a base substrate, an insulating film formed on the substrate, an undoped first and lattice-relaxed semiconductor layer formed on the insulating film, a second semiconductor layer having a tensile strain and formed on the first semiconductor layer, and a MISFET formed on the second semiconductor layer. Since the MISFET is formed in a strained Si layer, electrons are prevented from scattering in a channel region, improving the electron mobility. Furthermore, since the MISFET is formed in a thin SOI layer having a thickness of 100 nm or less, it is possible to reduce a parasitic capacitance in addition to the improvement of the electron mobility. As a result, the MISFET excellent in drivability can be obtained.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: February 10, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Usuda, Shinichi Takagi
  • Patent number: 6500735
    Abstract: There is disclosed a method of manufacturing a semiconductor device, wherein a semiconductor layer having an acute projection containing polycrystalline silicon is formed on a substrate, and then, an insulating layer is formed on the semiconductor layer through an oxidation of the semiconductor layer by excited oxygen species in such a manner that a radius of curvature of the acute projection of the semiconductor layer becomes 20 nm or more.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: December 31, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Koji Usuda
  • Publication number: 20020039831
    Abstract: There is disclosed a method of manufacturing a semiconductor device, wherein a semiconductor layer having an acute projection containing polycrystalline silicon is formed on a substrate, and then, an insulating layer is formed on the semiconductor layer through an oxidation of the semiconductor layer by excited oxygen species in such a manner that a radius of curvature of the acute projection of the semiconductor layer becomes 20 nm or more.
    Type: Application
    Filed: August 30, 2001
    Publication date: April 4, 2002
    Inventor: Koji Usuda
  • Patent number: 6066571
    Abstract: A method of preparing a semiconductor work surface comprises the steps of forming an Si monocrystaline substrate including a semiconductor work surface, removing by wet-etching a silicon oxide film formed on the work surface, using HF solution, and washing the work surface by pure water, serving as a washing liquid, of a dissolved oxygen concentration of 500 ppb or lower. The work surface is made of monocrystal and has an orientation a certain amount off the (001) plane. The certain amount is set such that an axis of the work surface has a component inclined with an angle of from 1.degree. to 5.degree. from the [001] direction to a <010> direction. The washing liquid of pure water has a property of etching the Si monocrystal, such that a single or a plurality of surfaces, including the (111) plane, can be preferentially exposed.
    Type: Grant
    Filed: January 8, 1998
    Date of Patent: May 23, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Usuda, Keisaku Yamada
  • Patent number: 4438449
    Abstract: A semiconductor device comprising a semiconductor element having an insulated gate electrode and a protective diode region provided in the neighborhood of the semiconductor element to protect the gate electrode from a dielectric breakdown; the diode is formed by a low resistivity semiconductor material to reduce its internal resistance, thereby accelerating the action of the protective diode so that the clamp action of the diode occurs earlier than the dielectric breakdown of the gate electrode.
    Type: Grant
    Filed: May 21, 1980
    Date of Patent: March 20, 1984
    Assignee: Hitachi, Ltd.
    Inventor: Koji Usuda
  • Patent number: 3999212
    Abstract: A semiconductor device comprising a semiconductor element having an insulated gate electrode and a protective diode region provided in the neighborhood of the semiconductor element to protect the gate electrode from a dielectric breakdown; the diode is formed by a low resistivity semiconductor material to reduce its internal resistance, thereby accelerating the action of the protective diode so that the clamp action of the diode occurs earlier than the dielectric breakdown of the gate electrode.
    Type: Grant
    Filed: June 26, 1970
    Date of Patent: December 21, 1976
    Assignee: Hitachi, Ltd.
    Inventor: Koji Usuda