Patents by Inventor Koji Yomogita

Koji Yomogita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100233877
    Abstract: A method of disposing a dummy pattern includes the steps of obtaining an inter-wiring parasitic capacity and a wiring total parasitic capacity for each wiring using wiring layout data and initial dummy pattern layout data; creating a first data base based on the inter-wiring parasitic capacity; creating a second data base based on the wiring total parasitic capacity; performing dynamic and static simulations for creating a third data base storing the results of the dynamic and static simulations, the result of the dynamic simulation being information about the first wiring, and the result of the static simulation being information about the second wiring; and performing an additional insertion of dummy pattern near a third wiring, the third wiring being determined to be a wiring which is capable of be affected by voltage noise based on the data in the third data base.
    Type: Application
    Filed: May 24, 2010
    Publication date: September 16, 2010
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Koji Yomogita
  • Patent number: 7743356
    Abstract: A method of disposing a dummy pattern includes the steps of obtaining an inter-wiring parasitic capacity and a wiring total parasitic capacity for each wiring using wiring layout data and initial dummy pattern layout data; creating a first data base based on the inter-wiring parasitic capacity; creating a second data base based on the wiring total parasitic capacity; performing dynamic and static simulations for creating a third data base storing the results of the dynamic and static simulations, the result of the dynamic simulation being information about the first wiring, and the result of the static simulation being information about the second wiring; and performing an additional insertion of dummy pattern near a third wiring, the third wiring being determined to be a wiring which is capable of be affected by voltage noise based on the data in the third data base.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: June 22, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Koji Yomogita
  • Publication number: 20060199284
    Abstract: A method of disposing a dummy pattern includes the steps of obtaining an inter-wiring parasitic capacity and a wiring total parasitic capacity for each wiring using wiring layout data and initial dummy pattern layout data; creating a first data base based on the inter-wiring parasitic capacity; creating a second data base based on the wiring total parasitic capacity; performing dynamic and static simulations for creating a third data base storing the results of the dynamic and static simulations, the result of the dynamic simulation being information about the first wiring, and the result of the static simulation being information about the second wiring; and performing an additional insertion of dummy pattern near a third wiring, the third wiring being determined to be a wiring which is capable of be affected by voltage noise based on the data in the third data base.
    Type: Application
    Filed: December 27, 2005
    Publication date: September 7, 2006
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Koji Yomogita