Abstract: A memory control part 12 cyclically assigns time slots to buffer memory parts 21 to 25 respectively and in each time slot, controls access between the corresponding buffer memory part and a synchronous RAM 11. A time slot is determined while assuming the worst case where access to the synchronous RAM is the severest. Time slot groups of [(the number of pixels on one horizontal scanning line)/256] in number are generated in an imaginary one horizontal scanning period, where [ ] denotes an integer portion of the number in the parentheses. For a buffer memory 22 whose data volume changes depending on a compression factor, a time slot ending point may be made variable, or a time slot may be generated by interrupt as an exception.

Abstract: A memory control part 12 cyclically assigns time slots to buffer memory parts 21 to 25 respectively and in each time slot, controls access between the corresponding buffer memory part and a synchronous RAM 11. A time slot is determined while assuming the worst case where access to the synchronous RAM is the severest. Time slot groups of [(the number of pixels on one horizontal scanning line)/256] in number are generated in an imaginary one horizontal scanning period, where [ ] denotes an integer portion of the number in the parentheses. For a buffer memory 22 whose data volume changes depending on a compression factor, a time slot ending point may be made variable, or a time slot may be generated by interrupt as an exception.

Abstract: A protocol control circuit for a data bus system in which data is communicated through a data bus and an acknowledgement signal is transmitted from a receiving unit through the data bus to a transmitting unit when data from the transmitting unit is received by the receiving unit. The protocol control circuit provides a buffer register unit including: a transmitting buffer register for storing at least one unit for data to be transmitted; an acknowledgement buffer register for storing the acknowledgement signal; and a selector connected to the transmitting buffer register and the acknowledgement buffer register. The selector carries out switching between the transmission of the output signal of the transmitting buffer register and the transmission of the output signal of the acknowledgement buffer register in correspondence with detection of proper timing of delivery of the acknowledgment signal.