Patents by Inventor Koji Yuki

Koji Yuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8283747
    Abstract: A semiconductor device including a first conduction type semiconductor layer; a second conduction type element forming region formed above the first conduction type semiconductor layer and formed with at least one semiconductor element formed on a surface region of the second conduction type element forming region; a first conduction type element-isolation region insulating and segregating the second conduction type element forming region from the exterior; and a second conduction type buried region formed at the interface of the first conduction type semiconductor layer and the second conduction type element forming region, formed separated from the first conduction type element-isolation region. In the semiconductor device a second conduction type high concentration region is buried in the surface of the second conduction type element forming region and formed to surround the semiconductor element and separated from the first conduction type element-isolation region.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: October 9, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Hiroyuki Tanaka, Takeshi Shimizu, Koji Yuki
  • Patent number: 8222703
    Abstract: A semiconductor device includes a semiconductor layer formed on an insulation layer and having an MOS (Metal Oxide Semiconductor) transistor area and a bi-polar transistor area; an MOS transistor formed in the MOS transistor area; and a bi-polar transistor formed in the bi-polar transistor area. The MOS transistor includes a source area of a second conductive type; a drain area of the second conductive type; and a channel area of a first conductive type. The MOS transistor further includes a gate electrode formed on the channel area with a first oxide layer inbetween. The bi-polar transistor includes a collector area of the second conductive type; an emitter area of the second conductive type; and a base area of the first conductive type. The bi-polar transistor further includes a dummy pattern formed on the base area with a second oxide layer inbetween.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: July 17, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Koichi Kishiro, Koji Yuki
  • Publication number: 20100052091
    Abstract: A semiconductor device including a first conduction type semiconductor layer; a second conduction type element forming region formed above the first conduction type semiconductor layer and formed with at least one semiconductor element formed on a surface region of the second conduction type element forming region; a first conduction type element-isolation region insulating and segregating the second conduction type element forming region from the exterior; and a second conduction type buried region formed at the interface of the first conduction type semiconductor layer and the second conduction type element forming region, formed separated from the first conduction type element-isolation region. In the semiconductor device a second conduction type high concentration region is buried in the surface of the second conduction type element forming region and formed to surround the semiconductor element and separated from the first conduction type element-isolation region.
    Type: Application
    Filed: August 17, 2009
    Publication date: March 4, 2010
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventors: Hiroyuki Tanaka, Takeshi Shimizu, Koji Yuki
  • Publication number: 20080237731
    Abstract: A semiconductor device includes a semiconductor layer formed on an insulation layer and having an MOS (Metal Oxide Semiconductor) transistor area and a bi-polar transistor area; an MOS transistor formed in the MOS transistor area; and a bi-polar transistor formed in the bi-polar transistor area. The MOS transistor includes a source area of a second conductive type; a drain area of the second conductive type; and a channel area of a first conductive type. The MOS transistor further includes a gate electrode formed on the channel area with a first oxide layer inbetween. The bi-polar transistor includes a collector area of the second conductive type; an emitter area of the second conductive type; and a base area of the first conductive type. The bi-polar transistor further includes a dummy pattern formed on the base area with a second oxide layer inbetween.
    Type: Application
    Filed: March 14, 2008
    Publication date: October 2, 2008
    Inventors: Koichi Kishiro, Koji Yuki
  • Publication number: 20070278542
    Abstract: There is provided a semiconductor device including: a semiconductor substrate including a supporting substrate, a first insulating film formed on the supporting substrate, and a silicon film having a first region and a second region formed on the first insulating film, and a third region at least a portion of which is disposed between the first region and the second region; a first diffusion layer formed on the first region of the silicon film and having a first conductive type; a second diffusion layer formed on the second region of the silicon film and containing impurities having a second conductive type, which has a polarity opposite to that of the first conductive type; a second insulating film formed on the third region of the silicon film; and a third insulating film formed on the second insulating film, as well as a method of fabricating the semiconductor device.
    Type: Application
    Filed: April 19, 2007
    Publication date: December 6, 2007
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Koji Yuki