Patents by Inventor Kojiro Horita

Kojiro Horita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10490445
    Abstract: When a void is caused in an interlayer insulating film on a semiconductor substrate, the invention prevents short circuit between two or more contact plugs that sandwich the void therebetween via a conductive film buried in the void at the time of formation of the contact plugs. An element isolation region having an upper surface lower than a main surface of the semiconductor substrate is formed inside a trench in the main surface of the semiconductor substrate, so that a void formed immediately above the semiconductor substrate in an active region and a void formed immediately above the element isolation region are divided from each other. In this manner, a conductive film is prevented from being buried in the second void.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: November 26, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takao Kamoshima, Kojiro Horita, Shuji Matsuo
  • Publication number: 20180090365
    Abstract: When a void is caused in an interlayer insulating film on a semiconductor substrate, the invention prevents short circuit between two or more contact plugs that sandwich the void therebetween via a conductive film buried in the void at the time of formation of the contact plugs. An element isolation region having an upper surface lower than a main surface of the semiconductor substrate is formed inside a trench in the main surface of the semiconductor substrate, so that a void formed immediately above the semiconductor substrate in an active region and a void formed immediately above the element isolation region are divided from each other. In this manner, a conductive film is prevented from being buried in the second void.
    Type: Application
    Filed: August 23, 2017
    Publication date: March 29, 2018
    Inventors: Takao KAMOSHIMA, Kojiro HORITA, Shuji MATSUO
  • Patent number: 5646694
    Abstract: A picture decoding apparatus has a memory for storing decoded picture data, three line buffers for temporarily storing picture data read from the memory, and a line buffer controller. Two of the three line buffers are selected sequentially and cyclically, and their operation modes are changed over to the writing mode, and decoded picture data read from the memory is stored sequentially in the two line buffers. The two line buffers are changed over from the writing mode to the reading mode sequentially and cyclically in the same order as that in which the two line buffers selected sequentially and cyclically were changed over to the writing mode, and data for one line is read sequentially from the two line buffers.
    Type: Grant
    Filed: November 13, 1995
    Date of Patent: July 8, 1997
    Assignees: Hitachi, Ltd., Sega Enterprises, Ltd.
    Inventors: Kojiro Horita, Junichi Kimura, Hirotaka Hara, Yutaka Okunoki