Abstract: The present disclosure relates to a solid-state imaging element in which the cost reduction of a curved imaging element can be achieved, a method for manufacturing the solid-state imaging element, and an electronic apparatus. A curvature base is formed so as to be curved in a concave shape at a center leaving a small edge. The curvature base is divided into five portions of an element disposition portion and four peripheral portions. This element disposition portion is formed in a porous state. A pore (air bubble) in the porous state is smaller than a pixel size. A porous material such as a ceramic-based material, a metal-based material, or a resin-based material can be used as the porous material, for example. The present disclosure can be applied to a CMOS solid-state imaging element to be used for an imaging device, for example.

Abstract: The present disclosure relates to a solid-state imaging element in which the cost reduction of a curved imaging element can be achieved, a method for manufacturing the solid-state imaging element, and an electronic apparatus. A curvature base is formed so as to be curved in a concave shape at a center leaving a small edge. The curvature base is divided into five portions of an element disposition portion and four peripheral portions. This element disposition portion is formed in a porous state. A pore (air bubble) in the porous state is smaller than a pixel size. A porous material such as a ceramic-based material, a metal-based material, or a resin-based material can be used as the porous material, for example. The present disclosure can be applied to a CMOS solid-state imaging element to be used for an imaging device, for example.

Abstract: Disclosed herein is an insulated gate field effect transistor including: (A) a source/drain region and a channel formation region; (B) a gate electrode formed above the channel formation region; and (C) a gate insulating film; wherein the gate insulating film is composed of a gate insulating film main body portion formed between the gate electrode and the channel formation region, and a gate insulating film extension portion extending from the insulating film main body portion to a middle of a side surface portion of the gate electrode, and when a height of the gate electrode is HGate and a height of the gate insulating film extension portion is HIns with a surface of the channel formation region as a reference, a relationship of HIns<HGate is fulfilled.

Abstract: Disclosed herein is a semiconductor device, including: an insulating film provided on a semiconductor substrate so as to have a trench pattern; a gate insulating film provided so as to cover an inner wall of the trench pattern; and a gate electrode formed so as to be filled in the trench pattern through the gate insulating film and so as to protrude more widely than the trench pattern on both sides of the trench pattern on the insulating film.

Abstract: Disclosed herein is a semiconductor device, including: an insulating film provided on a semiconductor substrate so as to have a trench pattern; a gate insulating film provided so as to cover an inner wall of the trench pattern; and a gate electrode formed so as to be filled in the trench pattern through the gate insulating film and so as to protrude more widely than the trench pattern on both sides of the trench pattern on the insulating film.

Abstract: Disclosed herein is an insulated gate field effect transistor including: (A) a source/drain region and a channel formation region; (B) a gate electrode formed above the channel formation region; and (C) a gate insulating film; wherein the gate insulating film is composed of a gate insulating film main body portion formed between the gate electrode and the channel formation region, and a gate insulating film extension portion extending from the insulating film main body portion to a middle of a side surface portion of the gate electrode, and when a height of the gate electrode is HGate and a height of the gate insulating film extension portion is HIns with a surface of the channel formation region as a reference, a relationship of HIns<HGate is fulfilled.

Abstract: The present invention provides a method of manufacturing a semiconductor device, in which while a conductive layer is formed on an oxide film formed as an insulating layer by using a CVD method, oxygen deficiency of the oxide film can be avoided without any drop in an dielectric breakdown resistance as the insulating layer of the oxide film and without any reduction in a long-term reliability. In this manufacturing method, when the conductive layer as a gate electrode is formed on the oxide film formed as a gate insulating layer, the conductive layer is formed in a non-reducing atmosphere.

Abstract: The present invention provides a method of manufacturing a semiconductor device, in which while a conductive layer is formed on an oxide film formed as an insulating layer by using a CVD method, oxygen deficiency of the oxide film can be avoided without any drop in an dielectric breakdown resistance as the insulating layer of the oxide film and without any reduction in a long-term reliability. In this manufacturing method, when the conductive layer as a gate electrode is formed on the oxide film formed as a gate insulating layer, the conductive layer is formed in a non-reducing atmosphere.