Patents by Inventor Kojiro Suzuki
Kojiro Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096524Abstract: An electronic component includes a ceramic body, and an external electrode on the ceramic body, the external electrode includes a base layer continuously covering an end surface of the ceramic body and a portion of a side surface bordering the end surface, and a plating layer covering the base layer, the ceramic body includes a recess open on the side surface, an opening of the recess includes a pair of edges, one edge of the opening is located within a covered region on the side surface covered with the base layer, and the other edge of the opening is spaced away from the covered region.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Inventors: Kojiro TOKIEDA, Hideyuki SUZUKI, Koichi YAMADA, Miki SASAKI
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Patent number: 11795528Abstract: Provided is an aluminum alloy material for die-casting that allows being manufactured at low-price and has a high strength property and a sufficient elongation property as an aluminum alloy, and a method for manufacturing the same. An aluminum alloy material for die-casting contains Si: 9.6 mass % to 12 mass %, Cu: 1.5 mass % to 3.5 mass %, Mg: more than 0.3 mass % to 1.6 mass %, Zn: 0.01 mass % to 3.5 mass %, Mn: 0.01 mass % to 0.7 mass %, Fe: 0.01 mass % to 1.3 mass %, and Al and inevitable impurities: balance when the aluminum alloy material for die-casting as a whole is 100 mass %, and a mass ratio of Fe to Mn (Fe/Mn) is 4.4 or less.Type: GrantFiled: September 29, 2022Date of Patent: October 24, 2023Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Kojiro Suzuki
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Publication number: 20230120599Abstract: Provided is an aluminum alloy material for die-casting that allows being manufactured at low-price and has a high strength property and a sufficient elongation property as an aluminum alloy, and a method for manufacturing the same. An aluminum alloy material for die-casting contains Si: 9.6 mass% to 12 mass%, Cu: 1.5 mass% to 3.5 mass%, Mg: more than 0.3 mass% to 1.6 mass%, Zn: 0.01 mass% to 3.5 mass%, Mn: 0.01 mass% to 0.7 mass%, Fe: 0.01 mass% to 1.3 mass%, and Al and inevitable impurities: balance when the aluminum alloy material for die-casting as a whole is 100 mass%, and a mass ratio of Fe to Mn (Fe/Mn) is 4.4 or less.Type: ApplicationFiled: September 29, 2022Publication date: April 20, 2023Inventor: Kojiro SUZUKI
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Patent number: 11593928Abstract: A manufacturing history management system according to an aspect of the present disclosure includes a data generation unit, a data storage unit, and a data extraction unit. The data generation unit generates manufacturing history data by associating internal void information specific to a product and manufacturing history information of the product with a product identification code. The data storage unit stores the manufacturing history data relating to a plurality of the products generated by the data generation unit. The data extraction unit checks the internal void information of the manufacturing history data of the plurality of products stored in the data storage unit against the internal void information of a predetermined product and extracts the manufacturing history data that matches the internal void information of the predetermined product from the manufacturing history data of the plurality of products stored in the data storage unit.Type: GrantFiled: October 27, 2020Date of Patent: February 28, 2023Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Kojiro Suzuki, Yuichi Furukawa
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Publication number: 20210142468Abstract: A manufacturing history management system according to an aspect of the present disclosure includes a data generation unit, a data storage unit, and a data extraction unit. The data generation unit generates manufacturing history data by associating internal void information specific to a product and manufacturing history information of the product with a product identification code. The data storage unit stores the manufacturing history data relating to a plurality of the products generated by the data generation unit. The data extraction unit checks the internal void information of the manufacturing history data of the plurality of products stored in the data storage unit against the internal void information of a predetermined product and extracts the manufacturing history data that matches the internal void information of the predetermined product from the manufacturing history data of the plurality of products stored in the data storage unit.Type: ApplicationFiled: October 27, 2020Publication date: May 13, 2021Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Kojiro Suzuki, Yuichi Furukawa
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Patent number: 10642562Abstract: A display apparatus includes a plurality of surfaces, and a display device provided on at least one surface among the plurality of surfaces. A plurality of communication sections are arranged to correspond to at least two or more side surfaces with respect to the surface on which the display device is provided among the plurality of surfaces and configured to perform communication within a predetermined distance, each of the plurality of communication sections including different identification information. A control section is configured to perform control of the plurality of communication sections and the display device. When another display apparatus is connected to the display apparatus, the control section periodically performs time synchronization to synchronize an image displayed on the display device with an image displayed on a display device provided in the other display apparatus.Type: GrantFiled: August 21, 2018Date of Patent: May 5, 2020Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yasuo Akatsuka, Masahiro Takagi, Hiroshi Tsurumi, Kojiro Suzuki, Koji Horisaki, Toshihiro Nakamura, Takashi Nakada
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Patent number: 10204043Abstract: According to one embodiment, a memory controller includes a compression unit and a padding processing unit. The compression unit generates first compressed data and second compressed data by compressing first data and second data. The padding processing unit pads first padding data for the first compressed data in accordance with a first padding pattern and pads second padding data for the second compressed data in accordance with a second padding pattern.Type: GrantFiled: February 1, 2017Date of Patent: February 12, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Keiri Nakanishi, Sho Kodama, Kohei Oikawa, Kojiro Suzuki
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Patent number: 10193579Abstract: According to an embodiment, a storage control device includes a controller, a compression condition determiner, a compressor, and an error correction encoder. The controller receives a write request for a data item and determines whether or not the wear degree of a target region in a storage device to which the data item is to be written is less than a threshold value. The compression condition determiner determines, based on the wear degree, an optimal compression condition out of compression conditions that include lossy compression. The compressor generates, based on the compression condition, compressed data. The error correction encoder subjects the data item to error correction and generates encoded data.Type: GrantFiled: September 7, 2016Date of Patent: January 29, 2019Assignee: Toshiba Memory CorporationInventors: Keiri Nakanishi, Katsuyuki Nomura, Sho Kodama, Youhei Fukazawa, Kazuki Inoue, Kojiro Suzuki, Harutaka Goto
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Publication number: 20180357035Abstract: A display apparatus includes a plurality of surfaces, and a display device provided on at least one surface among the plurality of surfaces. A plurality of communication sections are arranged to correspond to at least two or more side surfaces with respect to the surface on which the display device is provided among the plurality of surfaces and configured to perform communication within a predetermined distance, each of the plurality of communication sections including different identification information. A control section is configured to perform control of the plurality of communication sections and the display device. When another display apparatus is connected to the display apparatus, the control section periodically performs time synchronization to synchronize an image displayed on the display device with an image displayed on a display device provided in the other display apparatus.Type: ApplicationFiled: August 21, 2018Publication date: December 13, 2018Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasuo AKATSUKA, Masahiro TAKAGI, Hiroshi TSURUMI, Kojiro SUZUKI, Koji HORISAKI, Toshihiro NAKAMURA, Takashi NAKADA
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Patent number: 10078485Abstract: According to an embodiment, a display block is a display apparatus including a plurality of surfaces. The display block includes a display device, a plurality of transmitting/receiving sections that perform communication within a predetermined distance, and a control section. The display device is provided on at least one surface of the plurality of surfaces. The plurality of transmitting/receiving sections are arranged to correspond to at least two or more side surfaces with respect to the surface on which the display device is provided among the plurality of surfaces. The control section performs control of the plurality of transmitting/receiving sections and the display device.Type: GrantFiled: March 4, 2016Date of Patent: September 18, 2018Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yasuo Akatsuka, Masahiro Takagi, Hiroshi Tsurumi, Kojiro Suzuki, Koji Horisaki, Toshihiro Nakamura, Takashi Nakada
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Patent number: 9971523Abstract: According to one embodiment, a memory controller includes a compression unit and a padding processing unit. The compression unit compresses first data to be written into a first page and second data to be written into a second page. The padding processing unit performs a padding processing such that the compressed first data is written into first memory cells, first padding data is written into second memory cells, the compressed second data is written into third memory cells, and second padding data is written into fourth memory cells.Type: GrantFiled: September 9, 2016Date of Patent: May 15, 2018Assignee: Toshiba Memory CorporationInventors: Sho Kodama, Keiri Nakanishi, Kohei Oikawa, Kojiro Suzuki
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Patent number: 9900011Abstract: According to one embodiment, a semiconductor apparatus includes a block and a controller. The block includes a logic circuit and a routing module. The routing module includes a plurality of first wiring lines, a plurality of second wiring lines, switches, and a wiring line switching circuit. The switches are arranged to perform connection and disconnection between the first wiring lines and the second wiring lines. The wiring line switching circuit is arranged to switch a wiring line for transmitting the signal, among the first wiring lines and the second wiring lines. The controller is arranged to control driving of the switches and the wiring line switching circuit.Type: GrantFiled: September 2, 2016Date of Patent: February 20, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Kazuki Inoue, Kohei Oikawa, Yukimasa Miyamoto, Kosuke Hatsuda, Shuou Nomura, Kojiro Suzuki
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Publication number: 20170262194Abstract: According to one embodiment, a memory controller includes a compression unit and a padding processing unit. The compression unit compresses first data to be written into a first page and second data to be written into a second page. The padding processing unit performs a padding processing such that the compressed first data is written into first memory cells, first padding data is written into second memory cells, the compressed second data is written into third memory cells, and second padding data is written into fourth memory cells.Type: ApplicationFiled: September 9, 2016Publication date: September 14, 2017Inventors: Sho Kodama, Keiri Nakanishi, Kohei Oikawa, Kojiro Suzuki
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Publication number: 20170262212Abstract: According to one embodiment, a memory controller includes a compression unit and a padding processing unit. The compression unit generates first compressed data and second compressed data by compressing first data and second data. The padding processing unit pads first padding data for the first compressed data in accordance with a first padding pattern and pads second padding data for the second compressed data in accordance with a second padding pattern.Type: ApplicationFiled: February 1, 2017Publication date: September 14, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Keiri NAKANISHI, Sho KODAMA, Kohei OIKAWA, Kojiro SUZUKI
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Publication number: 20170257099Abstract: According to one embodiment, a semiconductor apparatus includes a block and a controller. The block includes a logic circuit and a routing module. The routing module includes a plurality of first wiring lines, a plurality of second wiring lines, switches, and a wiring line switching circuit. The switches are arranged to perform connection and disconnection between the first wiring lines and the second wiring lines. The wiring line switching circuit is arranged to switch a wiring line for transmitting the signal, among the first wiring lines and the second wiring lines. The controller is arranged to control driving of the switches and the wiring line switching circuit.Type: ApplicationFiled: September 2, 2016Publication date: September 7, 2017Inventors: Kazuki Inoue, Kohei Oikawa, Yukimasa Miyamoto, Kosuke Hatsuda, Shuou Nomura, Kojiro Suzuki
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Patent number: 9641850Abstract: With a video compression device configured to compress one pixel per cycle, a predictive pixel generation unit generates predictive pixel values of a plurality of predictive modes defined assuming local decode pixels read from predetermined positions of a line memory as upper reference pixels and an input original image pixel positioned on the left side of a pixel to be compressed as a left reference pixel for the pixel to be compressed. A predictive mode determination unit calculates a predictive error in a unit based on differential values between the pixel value to be compressed and the predictive pixel value, and selects a minimum predictive mode. A DPCM unit generates a minimum differential value between the minimum predictive pixel value and the pixel to be compressed assuming local decode pixels as upper reference pixels and a local decode pixel value one cycle before as a left reference pixel.Type: GrantFiled: April 30, 2014Date of Patent: May 2, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Keiri Nakanishi, Masashi Jobashi, Kojiro Suzuki
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Publication number: 20170070244Abstract: According to an embodiment, a storage control device includes a controller, a compression condition determiner, a compressor, and an error correction encoder. The controller receives a write request for a data item and determines whether or not the wear degree of a target region in a storage device to which the data item is to be written is less than a threshold value. The compression condition determiner determines, based on the wear degree, an optimal compression condition out of compression conditions that include lossy compression. The compressor generates, based on the compression condition, compressed data. The error correction encoder subjects the data item to error correction and generates encoded data.Type: ApplicationFiled: September 7, 2016Publication date: March 9, 2017Inventors: Keiri Nakanishi, Katsuyuki Nomura, Sho Kodama, Youhei Fukazawa, Kazuki Inoue, Kojiro Suzuki, Harutaka Goto
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Publication number: 20160266859Abstract: According to an embodiment, a display block is a display apparatus including a plurality of surfaces. The display block includes a display device, a plurality of transmitting/receiving sections that perform communication within a predetermined distance, and a control section. The display device is provided on at least one surface of the plurality of surfaces. The plurality of transmitting/receiving sections are arranged to correspond to at least two or more side surfaces with respect to the surface on which the display device is provided among the plurality of surfaces. The control section performs control of the plurality of transmitting/receiving sections and the display device.Type: ApplicationFiled: March 4, 2016Publication date: September 15, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasuo AKATSUKA, Masahiro TAKAGI, Hiroshi TSURUMI, Kojiro SUZUKI, Koji HORISAKI, Toshihiro NAKAMURA, Takashi NAKADA
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Publication number: 20140334541Abstract: With a video compression device configured to compress one pixel per cycle, a predictive pixel generation unit generates predictive pixel values of a plurality of predictive modes defined assuming local decode pixels read from predetermined positions of a line memory as upper reference pixels and an input original image pixel positioned on the left side of a pixel to be compressed as a left reference pixel for the pixel to be compressed. A predictive mode determination unit calculates a predictive error in a unit based on differential values between the pixel value to be compressed and the predictive pixel value, and selects a minimum predictive mode. A DPCM unit generates a minimum differential value between the minimum predictive pixel value and the pixel to be compressed assuming local decode pixels as upper reference pixels and a local decode pixel value one cycle before as a left reference pixel.Type: ApplicationFiled: April 30, 2014Publication date: November 13, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Keiri Nakanishi, Masashi Jobashi, Kojiro Suzuki
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Publication number: 20140285681Abstract: A multi-view imaging apparatus of an embodiment includes a plurality of imaging units each including an image sensor and a memory configured to store therein image data taken by the image sensor, the imaging units being daisy-chain connected to each other in order to send the image data, and also includes an interface unit connected to a lowermost imaging unit, the interface unit being configured to output pieces of image data taken by the plurality of imaging units to an outside. The imaging units each add own-stage data to data outputted from an upper-stage imaging unit, and output the resultant data to a lower-stage imaging unit.Type: ApplicationFiled: August 26, 2013Publication date: September 25, 2014Inventors: Kazuyo KANOU, Katsuyuki KIMURA, Yosuke BANDO, Kojiro SUZUKI, Hideho ARAKIDA, Fumihiko HYUGA, Kiwamu WATANABE, Hajime MATSUI, Atsushi MOCHIZUKI, Sho KODAMA, Akira MORIYA