Abstract: A semiconductor manufacturing method is mainly contemplated, improved to prevent an altered surface layer of a resist from being removed when a single patterned resist is used to provide dry-etch and wet-etch successively. On a semiconductor substrate an insulation film and a conductive layer are formed successively. On the conductive layer a patterned resist is formed. With the patterned resist used as a mask, the conductive layer is dry-etched. A surface layer of the patterned resist is partially removed. With the patterned resist used as a mask, the insulation film is wet-etched.

Abstract: After forming a phosphor-doped amorphous silicon film and before forming a bottom silicon oxide film, a heat treatment is performed while exhausting a gas from the vicinity of the silicon substrate. The heat treatment is performed at a temperature equal to or higher than that for forming the bottom silicon oxide film and at a pressure equal to or lower than that for forming the bottom silicon oxide film. Alternatively, after forming the phosphor-doped amorphous silicon film and before forming the bottom silicon oxide film, a TEOS oxide film and a phosphor-doped amorphous silicon film deposited on the back surface of the silicon substrate are removed. Further alternatively, these films deposited on the back surface of the silicon substrate are covered with a film which prevents gas desorption under the film formation condition for the bottom silicon oxide film.

Abstract: A semiconductor device as well as a method of manufacturing a semiconductor device wherein a wide trench separation band is formed without causing the scooping out of the silicon substrate can be gained. The process is provided with the step of forming a multilayer film on a silicon substrate, the step of patterning the multilayer film and of etching the silicon substrate so as to create a trench, the step of forming an inner wall silicon oxide film on the inner wall surface of the trench, the step of forming a trench oxide layer so as to fill in the trench, the step of polishing the trench oxide layer through CMP polishing so as to expose the silicon nitride layer and the step of etching the trench oxide film, which has undergone the CMP polishing, by a thickness no more than the thickness of the inner wall silicon oxide film.

Abstract: After forming a phosphor-doped amorphous silicon film (9) and before forming a bottom silicon oxide film, a heat treatment is performed while exhausting a gas from the vicinity of the silicon substrate (1). The heat treatment is performed at a temperature equal to or higher than that for forming the bottom silicon oxide film and at a pressure equal to or lower than that for forming the bottom silicon oxide film. Alternatively, after forming the phosphor-doped amorphous silicon film (9) and before forming the bottom silicon oxide film, a TEOS oxide film (601) and a phosphor-doped amorphous silicon film (901) deposited on the back surface of the silicon substrate (1) are removed. Further alternatively, these films deposited on the back surface of the silicon substrate (1) are covered with a film which prevents gas desorption under the film formation condition for the bottom silicon oxide film.

Abstract: A method of producing a semiconductor device having a multilayered wiring conductors and a system for producing the same. The nonuniformity of SOG coating film effectively suppressed and various treatments are simple and less time-consuming. A wiring conductor is formed on a semiconductor substrate, and an insulating layer covering the wiring conductor and the semiconductor substrate is formed, and the insulating layer is then subjected to a wet etching prior to the formation of SOG layer, thereby to increase a wettabiltity by the coating solution on the insulating layer.

Abstract: A semiconductor manufacturing method is mainly contemplated, improved to prevent an altered surface layer of a resist from being removed when a single patterned resist is used to provide dry-etch and wet-etch successively. On a semiconductor substrate an insulation film and a conductive layer are formed successively. On the conductive layer a patterned resist is formed. With the patterned resist used as a mask, the conductive layer is dry-etched. A surface layer of the patterned resist is partially removed. With the patterned resist used as a mask, the insulation film is wet-etched.

Abstract: A semiconductor device as well as a method of manufacturing a semiconductor device wherein a wide trench separation band is formed without causing the scooping out of the silicon substrate can be gained.

Abstract: A semiconductor manufacturing method is mainly contemplated, improved to prevent an altered surface layer of a resist from being removed when a single patterned resist is used to provide dry-etch and wet-etch successively. On a semiconductor substrate an insulation film and a conductive layer are formed successively. On the conductive layer a patterned resist is formed. With the patterned resist used as a mask, the conductive layer is dry-etched. A surface layer of the patterned resist is partially removed. With the patterned resist used as a mask, the insulation film is wet-etched.

Abstract: A method of producing a semiconductor device having a multilayered wiring conductors and a system for producing the same. The nonuniformity of SOG coating film effectively suppressed and various treatments are simple and less time-consuming. A wiring conductor is formed on a semiconductor substrate, and an insulating layer covering the wiring conductor and the semiconductor substrate is formed, and the insulating layer is then subjected to a wet etching prior to the formation of SOG layer, thereby to increase a wettabiltity by the coating solution on the insulating layer.

Abstract: A semiconductor device, in a circuit configuration on a semiconductor substrate, is disclosed which comprises: a boosting circuit for boosting an external power supply voltage to a plus voltage and a minus voltage; and a detecting circuit having a resistor formed of an impurity diffused layer so that the plus voltage and the minus voltage boosted by the boosting circuit is connected to the resistor, respectively to detect a potential at a prescribed point so as to verify if or not the boosting circuit has generated a desired potential.

Abstract: A field oxide film which is fine and having smaller upheaval of a bird's head is formed, so as to improve electrical characteristic of a conductive layer formed with end portions positioned on the field oxide film. A planarizing silicon film is formed on a silicon nitride film and a thermal oxide film, so as to planarize a concave generated between the thermal oxide film and a silicon nitride film. The planarizing silicon film is thermally oxidized, so as to form a planarizing thermal oxide film integrated with the thermal oxide film. Thereafter, the planarizing thermal oxide film is etched back to form the field oxide film, and the silicon nitride film and a polycrystalline silicon film are removed. Thereafter, the conductive layer with end portions positioned on the field oxide film is formed.

Abstract: A semiconductor device, including a circuit configuration formed on a semiconductor substrate, comprises: a boosting circuit for boosting an external power supply voltage to a plus voltage and a minus voltage; and a detecting circuit having a resistor formed of an impurity diffused layer so that the plus voltage and the minus voltage boosted by the boosting circuit are respectively connected to the resistor, to detect a potential at a prescribed point of said resistor so as to verify whether or not the boosting circuit has generated a desired potential.

Abstract: A p-type well and an n-type well surrounding the p-type well are formed in a p-type semiconductor substrate under a field insulating film. A polysilicon resistance film is formed on the field insulating film simultaneously with a floating gate formed in a memory cell region. A polycide conductive film is formed on a interlayer insulating film simultaneously with an auxiliary bit line formed in the memory cell region, and the polycide conductive film is connected to the resistance film by a contact formed in a via hole. A wiring line formed on an interlayer insulating film is connected to the polycide conductive film by a contact formed in a via hole penetrating the interlayer insulating film. The two via holes are formed at positions corresponding to regions in the p-type well. A negative voltage is applied to the wiring line, and the potential of a predetermined point on the resistance film is measured.

Abstract: A static random access memory (SRAM) is disclosed having a single bit line configuration. One memory cell includes access gate transistors Q5, Q6 connected in series between a data storage circuit 1 and a single bit line BL. In a writing operation, the gate electrodes of the transistors Q5, Q6 are boosted to a level exceeding the supply voltage by a X word line boosting circuit 7 and a Y word line boosting circuit 8 to bring the data storage circuit to an unstable data storage state in a memory cell selected by a row address signal and a column address signal. Data writing is carried out only in a desired memory cell, and erroneous data writing to other memory cells is prevented.

Abstract: A static random access memory (SRAM) is disclosed having a single bit line configuration. One memory cell includes access gate transistors Q5, Q6 connected in series between a data storage circuit 1 and a single bit line BL. In a writing operation, the gate electrodes of the transistors Q5, Q6 are boosted to a level exceeding the supply voltage by a X word line boosting circuit 7 and a Y word line boosting circuit 8 to bring the data storage circuit to an unstable data storage state in a memory cell selected by a row address signal and a column address signal. Data writing is carried out only in a desired memory cell, and erroneous data writing to other memory cells is prevented.

Abstract: A static random access memory (SRAM) is disclosed having a single bit line configuration. One memory cell includes access gate transistors Q5, Q6 connected in series between a data storage circuit 1 and a single bit line BL. In a writing operation, the gate electrodes of the transistors Q5, Q6 are boosted to a level exceeding the supply voltage by a X word line boosting circuit 7 and a Y word line boosting circuit 8 to bring the data storage circuit to an unstable data storage state in a memory cell selected by a row address signal and a column address signal. Data writing is carried out only in a desired memory cell, and erroneous data writing to other memory cells is prevented.