Patents by Inventor Koju Aoki
Koju Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7857505Abstract: A method and circuit for preventing an output signal, which has been corrected through digital correction or analog correction, from deviating from a target value and for preventing power supply noise and power consumption from increasing. A sensor amplification circuit receives output of a sensor as an input signal. Correction points are set at predetermined temperature intervals. The sensor amplification circuit performs digital correction for correcting the input signal with correction data set for each correction point. Further, the sensor amplification circuit performs a second correction for correcting the input signal between the correction points with gradient data calculated from the correction data for two of the correction points that are adjacent to each other.Type: GrantFiled: November 14, 2006Date of Patent: December 28, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Hiroyuki Sakima, Koju Aoki, Takahiro Watai, Masaya Mizutani, Takuya Okajima
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Patent number: 7622760Abstract: An n-well is formed in a p-type semiconductor substrate. A gate insulative film is formed to the p-type semiconductor substrate and the n-well, and a gate electrode is formed on the gate insulative film. A source layer selectively diffused with n-type impurities at high concentration is formed adjacent to the gate insulative film on the surface of the p-type semiconductor substrate, the n-well and a region extending on both of them. Further, a contact layer selectively diffused with p-type impurities at high concentration is formed being spaced from the source layer. A capacitance characteristic of good linearity over a wide range relative to the inter-terminal voltage VT can be obtained by applying an inter-terminal voltage VT between the source layer and the gate electrode.Type: GrantFiled: February 2, 2005Date of Patent: November 24, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Takaoki Ogawa, Kazuhiro Tomita, Koju Aoki
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Patent number: 7573970Abstract: A prescaler that operates in a broad band. The prescaler includes a buffer and a counter. The buffer includes a first amplification circuit, which has three inverter circuits of different drive capacities, a second amplification circuit, which has four series-connected inverter circuits, and a feedback circuit. One of the inverter circuits is connected between a capacitor and an inverter circuit via a first switch circuit and a second switch circuit. This varies the drive capacity of the first amplification circuit. The feedback circuit functions as a variable resistor having two transistors.Type: GrantFiled: August 28, 2006Date of Patent: August 11, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Katashi Hasegawa, Koju Aoki, Hiroshi Baba
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Patent number: 7345536Abstract: An amplifier circuit which is connected to a sensor and variably sets an amplification property and a control method thereof are disclosed, the circuit having the capability of restricting the influence of change with time and temperature change. The amplifier circuit 1, which receives, as an input, a detection signal from the sensor and variably sets an amplification property, comprises: (1) a first reference value retaining unit 50 for retaining a first reference value K1 for setting an amplification property which makes an output signal be a specified detection reference output voltage when a reference input condition KJ is detected; (2) a correction signal generation unit 30 for generating a correction signal HS which reduces the difference between an amplification property actual measurement value and an amplification property set value; and (3) a first amplification property correction unit 40 for correcting the first reference value K1 based on the correction signal HS.Type: GrantFiled: July 15, 2005Date of Patent: March 18, 2008Assignee: Fujitsu LimitedInventors: Masaya Mizutani, Koju Aoki, Takahiro Watai, Koji Takekawa, Hiroyuki Sakima
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Publication number: 20070229120Abstract: A temperature characteristic correction method enabling easy setting of correction points, while reducing deviations of an output signal from a target value and preventing power supply noise and power consumption from increasing. The method includes storing correction patterns, each of which includes correction points set at a temperature interval that differs between the correction patterns. The method further includes storing correction data for each correction point in each correction pattern, selecting a correction pattern corresponding to the temperature dependent characteristic of the input signal from the correction patterns, and correcting the temperature dependent characteristic of the input signal with the selected correction pattern and the correction data corresponding to the selected correction pattern.Type: ApplicationFiled: August 29, 2006Publication date: October 4, 2007Inventors: Takuya Okajima, Koju Aoki, Takahiro Watai, Masaya Mizutani, Hiroyuki Sakima
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Publication number: 20070223648Abstract: A prescaler that operates in a broad band. The prescaler includes a buffer and a counter. The buffer includes a first amplification circuit, which has three inverter circuits of different drive capacities, a second amplification circuit, which has four series-connected inverter circuits, and a feedback circuit. One of the inverter circuits is connected between a capacitor and an inverter circuit via a first switch circuit and a second switch circuit. This varies the drive capacity of the first amplification circuit. The feedback circuit functions as a variable resistor having two transistors.Type: ApplicationFiled: August 28, 2006Publication date: September 27, 2007Inventors: Katashi Hasegawa, Koju Aoki, Hiroshi Baba
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Publication number: 20070214884Abstract: A method and circuit for preventing an output signal, which has been corrected through digital correction or analog correction, from deviating from a target value and for preventing power supply noise and power consumption from increasing. A sensor amplification circuit receives output of a sensor as an input signal. Correction points are set at predetermined temperature intervals. The sensor amplification circuit performs digital correction for correcting the input signal with correction data set for each correction point. Further, the sensor amplification circuit performs a second correction for correcting the input signal between the correction points with gradient data calculated from the correction data for two of the correction points that are adjacent to each other.Type: ApplicationFiled: November 14, 2006Publication date: September 20, 2007Inventors: Hiroyuki Sakima, Koju Aoki, Takahiro Watai, Masaya Mizutani, Takuya Okajima
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Patent number: 7271595Abstract: Provided are two monitor circuits for monitoring two input signals of an input stage differential amplifier, respectively, and two monitor circuit for monitoring two output signals of the input stage differential amplifier, respectively. When failure occurs at the bridge circuit of a sensor element or at the input stage differential amplifier, the monitoring units or the monitoring units detect abnormality, which makes it possible to detect the failure of the sensor element or the input stage differential amplifier. Therefore it is possible to detect failure such as a disconnection or a short circuit of the bridge circuit of the sensor element and failure which has occurred at the amplifier for amplifying outputs of the sensor element.Type: GrantFiled: February 27, 2006Date of Patent: September 18, 2007Assignee: Fujitsu LimitedInventors: Katsuya Shimizu, Hiroyuki Sakima, Takahiro Watai, Masaya Mizutani, Koju Aoki, Koji Takekawa
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Publication number: 20070115005Abstract: Provided are two monitor circuits for monitoring two input signals of an input stage differential amplifier, respectively, and two monitor circuit for monitoring two output signals of the input stage differential amplifier, respectively. When failure occurs at the bridge circuit of a sensor element or at the input stage differential amplifier, the monitoring units or the monitoring units detect abnormality, which makes it possible to detect the failure of the sensor element or the input stage differential amplifier. Therefore it is possible to detect failure such as a disconnection or a short circuit of the bridge circuit of the sensor element and failure which has occurred at the amplifier for amplifying outputs of the sensor element.Type: ApplicationFiled: February 27, 2006Publication date: May 24, 2007Inventors: Katsuya Shimizu, Hiroyuki Sakima, Takahiro Watai, Masaya Mizutani, Koju Aoki, Koji Takekawa
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Publication number: 20060208795Abstract: An amplifier circuit which is connected to a sensor and variably sets an amplification property and a control method thereof are disclosed, the circuit having the capability of restricting the influence of change with time and temperature change. The amplifier circuit 1, which receives, as an input, a detection signal from the sensor and variably sets an amplification property, comprises: (1) a first reference value retaining unit 50 for retaining a first reference value K1 for setting an amplification property which makes an output signal be a specified detection reference output voltage when a reference input condition KJ is detected; (2) a correction signal generation unit 30 for generating a correction signal HS which reduces the difference between an amplification property actual measurement value and an amplification property set value; and (3) a first amplification property correction unit 40 for correcting the first reference value K1 based on the correction signal HS.Type: ApplicationFiled: July 15, 2005Publication date: September 21, 2006Inventors: Masaya Mizutani, Koju Aoki, Takahiro Watai, Koji Takekawa, Hiroyuki Sakima
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Patent number: 7064645Abstract: The present invention realizes a miniaturized electronic device that is still capable of maintaining its high reliability even when miniaturized. To this end, the electronic device has an electronic circuit, comprising: a substrate with a circuit formation surface on which one part of the electronic circuit is formed; a polyimide layer that is formed on the circuit formation surface; and a spiral inductor constituting another part of the electronic circuit, which is formed into a pattern on the polyimide layer.Type: GrantFiled: December 13, 2002Date of Patent: June 20, 2006Assignee: Fujitsu LimitedInventors: Kazuhiko Kobayashi, Hideharu Sakoda, Hirohisa Matsuki, Osamu Igawa, Mitsutaka Sato, Koju Aoki, Hiroyuki Sakima
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Publication number: 20050127411Abstract: An n-well is formed in a p-type semiconductor substrate. A gate insulative film is formed to the p-type semiconductor substrate and the n-well, and a gate electrode is formed on the gate insulative film. A source layer selectively diffused with n-type impurities at high concentration is formed adjacent to the gate insulative film on the surface of the p-type semiconductor substrate, the n-well and a region extending on both of them. Further, a contact layer selectively diffused with p-type impurities at high concentration is formed being spaced from the source layer. A capacitance characteristic of good linearity over a wide range relative to the inter-terminal voltage VT can be obtained by applying an inter-terminal voltage VT between the source layer and the gate electrode.Type: ApplicationFiled: February 2, 2005Publication date: June 16, 2005Inventors: Takaoki Ogawa, Kazuhiro Tomita, Koju Aoki
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Patent number: 6864729Abstract: A method of switching the mode of a PLL circuit which has a high-speed mode and a normal mode, which allows the PLL circuit to be locked up at a high speed. The PLL circuit includes a phase comparator and a charge pump for generating a current depending on a comparison output signal from the phase comparator. The mode switching method includes the steps of detecting whether a current output terminal of the charge pump is in a high impedance state, and switching the mode of the PLL circuit from the high-speed mode to the normal mode or from the normal mode to the high-speed mode when the high impedance state is detected.Type: GrantFiled: March 1, 2002Date of Patent: March 8, 2005Assignee: Fujitsu LimitedInventors: Koju Aoki, Hiroyuki Sakima
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Patent number: 6795516Abstract: A reset circuit for a PLL frequency synthesizer allows the PLL to quickly generate an output signal after waking up from a power-save mode. The reset circuit includes a delay circuit for receiving a shift signal and generating the output signal by delaying the shift signal for a predetermined time. A determination signal receives the shift signal and the output signal, determines whether they match, and generates a reset signal from the predetermined time when the shift signal is being shifted. A control circuit receives a power-save signal, which deactivates the PLL, and provides the delay circuit with a control signal for matching the output signal with the shift signal when the power-save signal is cancelled.Type: GrantFiled: March 10, 2000Date of Patent: September 21, 2004Assignee: Fujitsu LimitedInventors: Koji Takekawa, Koju Aoki
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Publication number: 20030127704Abstract: The present invention realizes a miniaturized electronic device that is still capable of maintaining its high reliability even when miniaturized. To this end, the electronic device has an electronic circuit, comprising: a substrate with a circuit formation surface on which one part of the electronic circuit is formed; a polyimide layer that is formed on the circuit formation surface; and a spiral inductor constituting another part of the electronic circuit, which is formed into a pattern on the polyimide layer.Type: ApplicationFiled: December 13, 2002Publication date: July 10, 2003Inventors: Kazuhiko Kobayashi, Hideharu Sakoda, Hirohisa Matsuki, Osamu Igawa, Mitsutaka Sato, Koju Aoki, Hiroyuki Sakima
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Patent number: 6525612Abstract: A mode control circuit of a PLL circuit for switching the PLL circuit from a high-speed mode to a normal mode. The PLL circuit compares the phase of a reference signal and the phase of a comparison signal to generate a first pulse signal and a second pulse signal, and generates based on the first and second pulse signals a frequency signal that is locked at a desired frequency. The mode control circuit receives the first and second pulse signals from the PLL circuit, generates a mode switch signal representing the normal mode when a difference between a phase of the first pulse signal and a phase of the second pulse signal is within a predetermined range, and, after the mode is switched from the high-speed mode to the normal mode, generates the mode switch signal such that the normal mode is maintained.Type: GrantFiled: January 10, 2001Date of Patent: February 25, 2003Assignee: Fujitsu LimitedInventor: Koju Aoki
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Publication number: 20020140470Abstract: A method of switching the mode of a PLL circuit which has a high-speed mode and a normal mode, which allows the PLL circuit to be locked up at a high speed. The PLL circuit includes a phase comparator and a charge pump for generating a current depending on a comparison output signal from the phase comparator. The mode switching method includes the steps of detecting whether a current output terminal of the charge pump is in a high impedance state, and switching the mode of the PLL circuit from the high-speed mode to the normal mode or from the normal mode to the high-speed mode when the high impedance state is detected.Type: ApplicationFiled: March 1, 2002Publication date: October 3, 2002Applicant: FUJITSU LIMITEDInventors: Koju Aoki, Hiroyuki Sakima
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Publication number: 20020005763Abstract: A mode control circuit of a PLL circuit for switching the PLL circuit from a high-speed mode to a normal mode. The PLL circuit compares the phase of a reference signal and the phase of a comparison signal to generate a first pulse signal and a second pulse signal, and generates based on the first and second pulse signals a frequency signal that is locked at a desired frequency. The mode control circuit receives the first and second pulse signals from the PLL circuit, generates a mode switch signal representing the normal mode when a difference between a phase of the first pulse signal and a phase of the second pulse signal is within a predetermined range, and, after the mode is switched from the high-speed mode to the normal mode, generates the mode switch signal such that the normal mode is maintained.Type: ApplicationFiled: January 10, 2001Publication date: January 17, 2002Applicant: Fujitsu LimitedInventor: Koju Aoki
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Patent number: 6181181Abstract: A phase shifter that may be used in a quadrature modulator or an image suppression mixer. The phase shifter includes a low pass filter that receives an input signal and generates a first carrier signal. A high pass filter also receives the input signal and generates a second carrier signal. A phase difference detection circuit connected to the high and low pass filters receives the first and second carrier signals and generates a control signal based on the phase difference between the carrier signals. The control signal is fed back to at least one of the low pass filter and the high pass filter to compensate for phase errors caused by parasitic capacitance. The phase shifter has a small circuit area and is very accurate, allowing it to be used in communications devices.Type: GrantFiled: March 2, 1999Date of Patent: January 30, 2001Assignee: Fujitsu LimitedInventors: Masahiro Tsukahara, Koju Aoki