Patents by Inventor Kok Chai Goh
Kok Chai Goh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088087Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Inventors: Alexander HEINRICH, Michael JUERSS, Konrad ROESL, Oliver EICHINGER, Kok Chai GOH, Tobias SCHMIDT
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Patent number: 11842975Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.Type: GrantFiled: November 11, 2019Date of Patent: December 12, 2023Assignee: Infineon Technologies AGInventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt
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Publication number: 20200075530Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.Type: ApplicationFiled: November 11, 2019Publication date: March 5, 2020Inventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt
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Patent number: 10475761Abstract: A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer.Type: GrantFiled: September 10, 2018Date of Patent: November 12, 2019Assignee: Infineon Technologies AGInventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt
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Publication number: 20190006311Abstract: A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer.Type: ApplicationFiled: September 10, 2018Publication date: January 3, 2019Inventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt
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Publication number: 20170025375Abstract: An electric device with a multi-layer contact is disclosed. In an embodiment, the electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.Type: ApplicationFiled: September 30, 2016Publication date: January 26, 2017Inventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt
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Patent number: 9490193Abstract: The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.Type: GrantFiled: December 1, 2011Date of Patent: November 8, 2016Assignee: Infineon Technologies AGInventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt
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Patent number: 9373609Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a semiconductor chip and a bump. The semiconductor chip has a contact pad on a major surface. The bump is disposed on the contact pad of the semiconductor chip. A solder layer is disposed on sidewalls of the bump.Type: GrantFiled: October 18, 2012Date of Patent: June 21, 2016Assignee: Infineon Technologies AGInventors: Meng Tong Ong, Thiam Huat Lim, Kok Chai Goh
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Patent number: 9275944Abstract: A semiconductor package includes a block having a first side, a second side opposite the first side and a recessed region extending from the second side toward the first side so that the block has a thinner part in the recessed region and a thicker part outside the recessed region. The semiconductor package further includes a first semiconductor die and a second semiconductor die each having opposing first and second sides. The first semiconductor die is disposed in the recessed region of the block and attached to the thinner part of the block at the first side of the first semiconductor die. The second semiconductor die is attached to the second side of the first semiconductor die at a first side of the second semiconductor die.Type: GrantFiled: August 29, 2013Date of Patent: March 1, 2016Assignee: Infineon Technologies AGInventor: Kok Chai Goh
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Patent number: 9209152Abstract: A method and apparatus for packaging a semiconductor chip is presented. A semiconductor device includes a chip, a lead, and an encapsulant. The encapsulant includes a stabilization layer, a laminate molding layer connected to the stabilization layer, and a conductive strip connected to the laminate molding layer. The conductive strip electrically connects the contact area of the chip to the lead.Type: GrantFiled: April 19, 2013Date of Patent: December 8, 2015Assignee: Infineon Technologies AGInventors: Kok Chai Goh, Meng Tong Ong
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Patent number: 9054063Abstract: A semiconductor package includes a single semiconductor die and an electrically and thermally conductive base. The single semiconductor die includes a semiconductor body having opposing first and second surfaces and insulated sides between the first and second surfaces. The single semiconductor die further includes a first electrode at the first surface and a second electrode at the second surface. The single semiconductor die has a defined thickness measured between the first and second surfaces, a defined width measured along one of the insulated sides, and a defined length measured along another one of the insulated sides. The base is attached to the second electrode at the second surface of the single semiconductor die and has the same length and width as the single semiconductor die.Type: GrantFiled: April 5, 2013Date of Patent: June 9, 2015Assignee: Infineon Technologies AGInventors: Kok Chai Goh, Meng Tong Ong
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Publication number: 20150061096Abstract: A semiconductor package includes a block having a first side, a second side opposite the first side and a recessed region extending from the second side toward the first side so that the block has a thinner part in the recessed region and a thicker part outside the recessed region. The semiconductor package further includes a first semiconductor die and a second semiconductor die each having opposing first and second sides. The first semiconductor die is disposed in the recessed region of the block and attached to the thinner part of the block at the first side of the first semiconductor die. The second semiconductor die is attached to the second side of the first semiconductor die at a first side of the second semiconductor die.Type: ApplicationFiled: August 29, 2013Publication date: March 5, 2015Inventor: Kok Chai Goh
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Publication number: 20140312497Abstract: A method and apparatus for packaging a semiconductor chip is presented. A semiconductor device includes a chip, a lead, and an encapsulant. The encapsulant includes a stabilization layer, a laminate molding layer connected to the stabilization layer, and a conductive strip connected to the laminate molding layer. The conductive strip electrically connects the contact area of the chip to the lead.Type: ApplicationFiled: April 19, 2013Publication date: October 23, 2014Applicant: Infineon Technologies AGInventors: Kok Chai Goh, Meng Tong Ong
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Publication number: 20140299981Abstract: A semiconductor package includes a single semiconductor die and an electrically and thermally conductive base. The single semiconductor die includes a semiconductor body having opposing first and second surfaces and insulated sides between the first and second surfaces. The single semiconductor die further includes a first electrode at the first surface and a second electrode at the second surface. The single semiconductor die has a defined thickness measured between the first and second surfaces, a defined width measured along one of the insulated sides, and a defined length measured along another one of the insulated sides. The base is attached to the second electrode at the second surface of the single semiconductor die and has the same length and width as the single semiconductor die.Type: ApplicationFiled: April 5, 2013Publication date: October 9, 2014Inventors: Kok Chai Goh, Meng Tong Ong
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Publication number: 20140110835Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a semiconductor chip and a bump. The semiconductor chip has a contact pad on a major surface. The bump is disposed on the contact pad of the semiconductor chip. A solder layer is disposed on sidewalls of the bump.Type: ApplicationFiled: October 18, 2012Publication date: April 24, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Meng Tong Ong, Thiam Huat Lim, Kok Chai Goh
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Publication number: 20130140685Abstract: The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.Type: ApplicationFiled: December 1, 2011Publication date: June 6, 2013Applicant: Infineon Technologies AGInventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt