Abstract: Communication circuitry having efficient utilization of transceiver and channel resources is described. The communication circuitry may dynamically reallocate transceiver resources assigned to protocol circuitry, such that it becomes available for other circuitry or for the interface of the transceiver circuitry. Multiplexers of the transceiver circuitry may be used in the reallocation of resources.

Abstract: Systems and techniques for configuration of a system on a programmable chip (SOPC) are described. By configuring the SOPC, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space.

Abstract: Systems and techniques for configuration of a system on a programmable chip (SOPC) are described. By configuring the SOPC, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space.

Abstract: Systems and techniques for configuration of a system on a programmable chip (SOPC) are described. By configuring the SOPC, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space.

Abstract: The present invention provide circuits, methods, and apparatus directed to an integrated circuit having a memory interface that is configurable to have one of a multiple different bus widths. The memory interface has a first set of lines and a second set of lines. The first and second set of lines are arranged such that there are multiple locations at which a via may be placed to connect a line of the first set to a line of the second set. The placement of the vias determines the bus width of the memory interface.

Abstract: Techniques and mechanisms generate a configuration bit stream to load into a circuit such as a Programmable Logic Device (PLD). A configuration bit stream may have a reduced size if “phantom bits” not corresponding to configuration elements are removed. However, the PLD may need a full-sized and properly ordered configuration bit stream in order to be properly configured. Techniques and mechanisms are described for selectively adding a “padding bit” to compensate for the missing phantom bits.

Abstract: Techniques and mechanisms generate a configuration bit stream to load into a circuit such as a Programmable Logic Device (PLD). A configuration bit stream may have a reduced size if “phantom bits” not corresponding to configuration elements are removed. However, the PLD may need a full-sized and properly ordered configuration bit stream in order to be properly configured. Techniques and mechanisms are described for selectively adding a “padding bit” to compensate for the missing phantom bits.

Abstract: A configurable memory circuit is provided. The memory circuit includes an inverter coupled to another inverter as back-to-back inverters. A programmable switch is placed on each side of the memory circuit. The programmable switches are used to configure the memory circuit. The memory circuit, depending on the configuration of the programmable switches and the back-to-back inverters, may operate as a ROM that stores a logic high value, a ROM that stores a logic low value, or a RAM.

Abstract: Techniques and mechanisms generate a configuration bit stream to load into a circuit such as a Programmable Logic Device (PLD). A configuration bit stream may have a reduced size if “phantom bits” not corresponding to configuration elements are removed. However, the PLD may need a full-sized and properly ordered configuration bit stream in order to be properly configured. Techniques and mechanisms are described for selectively adding a “padding bit” to compensate for the missing phantom bits.

Abstract: Multiplier-accumulator circuitry includes circuitry for forming a plurality of partial products of multiplier and multiplicand inputs, carry-save adder circuitry for adding together the partial products and another input to produce intermediate sum and carry outputs, final adder circuitry for adding together the intermediate sum and carry outputs to produce a final output, and feedback circuitry for applying the final output (typically after some delay, e.g., due to registration of the final output) to the carry-save adder circuitry as said another input. The above circuitry may be implemented in so-called “hard IP” (intellectual property) of a field-programmable gate array (“FPGA”) integrated circuit device. If desired, any overflow from the accumulation performed by the above circuitry may be accumulated in “soft” accumulator-overflow circuitry that is implemented in the general-purpose programmable logic of the FPGA.

Abstract: Systems and techniques for configuration of a system on a programmable chip (SOPC) are described. By configuring the SOPC, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space.

Abstract: Memory performance in programmable logic is significantly increased by adjusting circuitry operation to adjust for variations in process, voltage, or temperature. A calibration circuit adjusts control signal timing, dynamically and automatically, to compensate real time to process, voltage, and temperature variation. A feedback system using a control block and a dummy mimicking concept are provided.

Abstract: The present invention provide circuits, methods, and apparatus directed to an integrated circuit having a memory interface that is configurable to have one of a multiple different bus widths. The memory interface has a first set of lines and a second set of lines. The first and second set of lines are arranged such that there are multiple locations at which a via may be placed to connect a line of the first set to a line of the second set. The placement of the vias determines the bus width of the memory interface.

Abstract: Memory performance in programmable logic is significantly increased by adjusting a timing of control signals sent to a memory to compensate for variations in process, voltage, or temperature. A calibration circuit can adjust the control signal timing, dynamically and automatically, to provide accurate and high performance memory operations. For example, timing settings for the control signals can be determined such that data written/read from the memory are accurate. The timing setting can also be changed to provide faster memory operations while still providing accuracy. A feedback system using a control block and a dummy mimicking concept are also provided.

Abstract: Techniques are provided for controlling an on-chip termination (OCT) in an output driver. The OCT control circuit calibrates the effective resistance of transistors in the output driver to match an external resistor using a feedback loop. The feedback loop monitors the output voltage and generates an analog calibration signal that varies the output impedance of a selected group of the output transistors that are enabled to drive the output terminal. Digital signals under the control of the user select the number of output transistors to be enabled based on the output driver requirements of the circuit. The analog calibration signal varies the signal level driving the selected output transistors to modify the effective output impedance of the circuit for better termination matching.

Abstract: A logic module for a structured ASIC is mask-programmable to perform any of a plurality of logic functions or to alternatively function as two static random access memory (“SRAM”) cells. Most or all of the circuitry needed to enable the logic module to function as SRAM cells is circuitry that is available for use in logic mode configuration of the module. Similarly, most or all of the logic circuitry of the logic module is put to use to provide the SRAM cells when the module is configured in SRAM mode. The circuitry of the logic module is therefore used very efficiently, whether the module is configured for logic mode or SRAM mode.

Abstract: The present invention provide circuits, methods, and apparatus directed to an integrated circuit having a memory interface that is configurable to have one of a multiple different bus widths. The memory interface has a first set of lines and a second set of lines. The first and second set of lines are arranged such that there are multiple locations at which a via may be placed to connect a line of the first set to a line of the second set. The placement of the vias determines the bus width of the memory interface.

Abstract: Dual port memory array circuitry is provided that includes bit line voltage clamping circuitry. The clamping circuitry contains control transistors that are used to enable and disable the clamping circuitry. The clamping circuitry also contains voltage regulator transistors and feedback paths. When a write operation is performed on one port of the dual port memory array while a read operation is being performed on the other port of the dual port memory array, the bit line voltage clamping circuitry prevents the voltages on the read port bit lines from dropping too low. This allows the write operation to be performed rapidly, even if the memory cell being written to has been adversely affected by variations due to process, voltage, and temperature.

Abstract: Programmable logic device integrated circuits with adjustable register and memory address decoder circuitry are provided. The integrated circuits contain programmable memory blocks and programmable logic that is configured by a user. Depending on the type of user logic that is implemented by the user, the programmable logic device integrated circuit may have different timing needs for its memory blocks. The adjustable register and memory address decoder circuitry has associated programmable elements that are loaded with configuration data. The configuration data adjusts the timing characteristics of the adjustable register and memory address decoder circuitry to accommodate the user logic. The adjustable register and memory address decoder circuitry may be used to make setup and clock-to-output timing adjustments to optimize a logic design.

Abstract: Dual port memory array circuitry is provided that includes bit line voltage clamping circuitry. The clamping circuitry contains control transistors that are used to enable and disable the clamping circuitry. The clamping circuitry also contains voltage regulator transistors and feedback paths. When a write operation is performed on one port of the dual port memory array while a read operation is being performed on the other port of the dual port memory array, the bit line voltage clamping circuitry prevents the voltages on the read port bit lines from dropping too low. This allows the write operation to be performed rapidly, even if the memory cell being written to has been adversely affected by variations due to process, voltage, and temperature.