Abstract: A controller for a brushless direct current (BLDC) motor includes a pulse width modulator and a control circuit. The pulse width modulator provides a plurality of phase control signals to control corresponding ones of a plurality of phases of the BLDC motor. The control circuit controls the pulse width modulator to provide pulses to the plurality of phases to control a speed of the BLDC motor by causing the pulse width modulator to adjust widths of the pulses when a measured current in an active one of a corresponding phase exceeds a threshold in a startup mode. In one form, the controller is part of a BLDC motor system which also includes a plurality of phase drivers each having inputs for receiving respective ones of said plurality of phase control signals, and outputs adapted to couple to corresponding phases of the BLDC motor.

Abstract: A controller for a BLDC motor includes a pulse width modulator and a control circuit. The pulse width modulator provides at least one phase control signal for a corresponding phase of the BLDC motor with a pulse width determined by a duty cycle signal. The duty cycle adjustment circuit has an input for receiving the at least one phase control signal, and an output for providing a corresponding modified phase control signal by adjusting widths of pulses of the at least one phase control signal when an average current in said corresponding phase exceeds a threshold.

Abstract: An apparatus includes a controller and a comparator. The controller generates pulse width modulation (PWM) signals to drive stator windings of a brushless direct current (BLDC) motor in a commutation sequence such that one of the stator windings at a given time is open; and generates a tracking signal synchronized to the PWM signals and indicative of times when a leakage current is present in the open stator winding. The comparator senses when a back electromotive force of the open stator winding has an associated zero crossing. The sensing by the comparator is selectively enabled and disabled by the tracking signal.

Abstract: A controller for a brushless direct current (BLDC) motor includes a pulse width modulator and a control circuit. The pulse width modulator provides a plurality of phase control signals to control corresponding ones of a plurality of phases of the BLDC motor. The control circuit controls the pulse width modulator to provide pulses to the plurality of phases to control a speed of the BLDC motor by causing the pulse width modulator to adjust widths of the pulses when a measured current in an active one of a corresponding phase exceeds a threshold in a startup mode. In one form, the controller is part of a BLDC motor system which also includes a plurality of phase drivers each having inputs for receiving respective ones of said plurality of phase control signals, and outputs adapted to couple to corresponding phases of the BLDC motor.

Abstract: An apparatus includes a controller and a comparator. The controller generates pulse width modulation (PWM) signals to drive stator windings of a brushless direct current (BLDC) motor in a commutation sequence such that one of the stator windings at a given time is open; and generates a tracking signal synchronized to the PWM signals and indicative of times when a leakage current is present in the open stator winding. The comparator senses when a back electromotive force of the open stator winding has an associated zero crossing. The sensing by the comparator is selectively enabled and disabled by the tracking signal.

Abstract: A controller for a BLDC motor includes a pulse width modulator and a control circuit. The pulse width modulator provides at least one phase control signal for a corresponding phase of the BLDC motor with a pulse width determined by a duty cycle signal. The duty cycle adjustment circuit has an input for receiving the at least one phase control signal, and an output for providing a corresponding modified phase control signal by adjusting widths of pulses of the at least one phase control signal when an average current in said corresponding phase exceeds a threshold.

Abstract: A wireless carrier sense multiple access/collision detection (CSMA/CD) communication system (1) is disclosed which includes a repeater station (R; 10) and a plurality of terminal stations (E, F, G; 30). A wireless uplink communication channel (Fu) provides for one-way communications between each terminal station and the repeater station and a wireless downlink communication channel (Fd) provides for one-way communications between the repeater station and each of the terminal station. The uplink and downlink communication channels operate at different transmission wavelengths. A bit pattern (18) received by the repeater station via the uplink channel is retransmitted via the downlink channel.