Abstract: A method of constructing a hierarchical clock tree for an integrated circuit may include constructing a clock distribution network on a first level, pushing the clock distribution network to a second level, implementing partition clock trees in partitions on the second level, and calculating combined timing of the clock distribution network and the partition clock trees on the second level. Implementing the partition clock trees may include constructing the partition dock trees in the partitions on the second level, calculating trial timing for the partition clock trees, calculating target timing constraints for the partition clock trees based on timing of the dock distribution network and the trial timing for the partition dock trees, and adjusting the timing of one or more of the partition clock trees based on the target constraints.

Abstract: A method of constructing a hierarchical clock tree for an integrated circuit may include constructing a clock distribution network on a first level, pushing the clock distribution network to a second level, implementing partition clock trees in partitions on the second level, and calculating combined timing of the clock distribution network and the partition clock trees on the second level. Implementing the partition clock trees may include constructing the partition dock trees in the partitions on the second level, calculating trial timing for the partition clock trees, calculating target timing constraints for the partition clock trees based on timing of the dock distribution network and the trial timing for the partition dock trees, and adjusting the timing of one or more of the partition clock trees based on the target constraints.

Abstract: A method of constructing a hierarchical clock tree for an integrated circuit may include constructing a clock distribution network on a first level, pushing the clock distribution network to a second level, implementing partition clock trees in partitions on the second level, and calculating combined timing of the clock distribution network and the partition clock trees on the second level. Implementing the partition clock trees may include constructing the partition clock trees in the partitions on the second level, calculating trial timing for the partition clock trees, calculating target timing constraints for the partition clock trees based on timing of the clock distribution network and the trial timing for the partition clock trees, and adjusting the timing of one or more of the partition clock trees based on the target constraints.

Abstract: A method of automatically constructing a hierarchical clock tree for an integrated circuit may include constructing a global clock tree on a first level based on first-level constraints, pushing the global clock tree to partitions on a second level, and generating second-level constraints for the partitions on the second level. The second-level constraints may be included in configuration files that may be generated for the partitions on the second level. The first-level constraints may be included in a first-level configuration file that is user-modifiable. The second-level constraints may include information for replicating multiple instantiated partitions on the second level. The method may further include modifying terminal names and/or configurations after pushdown. The method may further include creating infrastructure to analyze timing of the global clock tree.

Abstract: A timing fixing logic section may select a timing path from among a plurality of timing paths. For the selected timing path, multiple nets along the path may be traversed. For a particular net, multiple metal layers may be traversed. For a particular metal layer, multiple shapes that are associated with the particular net may be traversed. A timing fixing logic section may examine space that is nearby each of the shapes, and identify unused space. The timing fixing logic section may add an extension metal section to the shape. In addition, the timing fixing logic section may identify an existing via of a first type, and select an alternate via of a second type having a resistance that is higher or lower than the existing via. The existing via may be replaced with the alternate via. Accordingly, hold and setup timing of a circuit may be improved.

Abstract: A timing fixing logic section may select a timing path from among a plurality of timing paths. For the selected timing path, multiple nets along the path may be traversed. For a particular net, multiple metal layers may be traversed. For a particular metal layer, multiple shapes that are associated with the particular net may be traversed. A timing fixing logic section may examine space that is nearby each of the shapes, and identify unused space. The timing fixing logic section may add an extension metal section to the shape. In addition, the timing fixing logic section may identify an existing via of a first type, and select an alternate via of a second type having a resistance that is higher or lower than the existing via. The existing via may be replaced with the alternate via. Accordingly, hold and setup timing of a circuit may be improved.

Abstract: A method of automatically constructing a hierarchical clock tree for an integrated circuit may include constructing a global clock tree on a first level based on first-level constraints, pushing the global clock tree to partitions on a second level, and generating second-level constraints for the partitions on the second level. The second-level constraints may be included in configuration files that may be generated for the partitions on the second level. The first-level constraints may be included in a first-level configuration file that is user-modifiable. The second-level constraints may include information for replicating multiple instantiated partitions on the second level. The method may further include modifying terminal names and/or configurations after pushdown. The method may further include creating infrastructure to analyze timing of the global clock tree.

Abstract: A method of constructing a hierarchical clock tree for an integrated circuit may include constructing a clock distribution network on a first level, pushing the clock distribution network to a second level, implementing partition clock trees in partitions on the second level, and calculating combined timing of the clock distribution network and the partition clock trees on the second level. Implementing the partition clock trees may include constructing the partition clock trees in the partitions on the second level, calculating trial timing for the partition clock trees, calculating target timing constraints for the partition clock trees based on timing of the clock distribution network and the trial timing for the partition clock trees, and adjusting the timing of one or more of the partition clock trees based on the target constraints.

Abstract: A carry lookahead adder is employed to determine an equality relationship and one or more inequality relationships between two operands. The carry lookahead adder includes a hierarchy of carry lookahead stages, each carry lookahead stage using either corresponding bits of the two operands or the carry generate values and carry propagate values from the prior stage to generate carry generate values and carry propagate values for use at the next stage. Equality logic receives a subset of the carry generate values and carry propagate values and, based on this subset of values, provides an equality relationship indicator that indicates the equality relationship between the two operands, or portions thereof. Further, inequality logic also receives a subset of the carry generate values and carry propagate values, and based on this subset of values, provides an inequality relationship indicator that indicates an inequality relationship between the two operands, or portions thereof.

Abstract: A clock switching technique allows selecting an input clock signal from two clock sources. The two clock sources are asynchronous to one another and a clock select signal is used to determine which of the clocks will be switched onto the clock output line. The clock select signal is asynchronous to both clock sources and can be either from a programmable bit implemented under software control or as a single signal generated from some other logic block. The technique guarantees that the switching to the desired clock based on the binary value of the clock select signal onto the clock line is glitch-free. The clock switching technique is independent of the two clock source frequencies as well as the system clock frequency.

Abstract: A clock switching technique allows selecting an input clock signal from any number of clock sources. Multiplexed input clock signals are switched on the fly onto an internal clock line coupled to an output clock line. Clock glitches are allowed on the output clock line. A clock invalid signal is asserted synchronous with the internal clock line during the time clock glitches may potentially be generated. The clock invalid signal signifies that clock switching is in progress and can be used to reset circuits which use the output clock line preventing problems in those circuits typically caused by clock glitches during the period of output clock instability. The clock switching technique is independent of clock source frequency as well as the system clock frequency.

Abstract: A clock switching technique allows selecting an input clock signal from two clock sources. The two clock sources are asynchronous to one another and a clock select signal is used to determine which of the clocks will be switched onto the clock output line. The clock select signal is asynchronous to both clock sources and can be either from a programmable bit implemented under software control or as a single signal generated from some other logic block. The technique guarantees that the switching to the desired clock based on the binary value of the clock select signal onto the clock line is glitch-free. The clock switching technique is independent of the two clock source frequencies as well as the system clock frequency.

Abstract: A programmable interrupt controller arrangement is provided including a multiple number of selectably enabled programmable interrupt controllers along with a multi-channel switch matrix. A scalable number of interrupt sources can be routed to any particular interrupt request line. In addition, from the same architecture, multiple interrupt sources are allowed to share any one of the interrupt request lines. Interrupt signals are routed via the switch matrix under software control. PC/AT compatibility is achieved by selectively disabling certain of the programmable interrupt controllers.

Abstract: A microcontroller is provided with one or more synchronous serial channels, such as HDLC channels, that are coupled to time slot assigners for communication over a time division multiplex bus. The time slot assigners each include a bit position start register and a bit position stop register that allows the time slot assigner to enable and disable the associated synchronous serial channel on the arrival of a specific bit position within the time division multiplex bus frame. Further, an end of slot adjust register provides for additional bits to be placed by the time slot assigner on to the end of a slot that is transmitted by an associated synchronous serial communication channel transmitter.