Abstract: An active interposer device includes a multiplexer circuit configurable to provide a first signal from a first integrated circuit to an external terminal of the active interposer device in a first configuration of the active interposer device. The multiplexer circuit is further configurable to provide a second signal from a second integrated circuit to the external terminal in a second configuration of the active interposer device. The second integrated circuit is larger than the first integrated circuit, and the active interposer device is configurable to couple the first integrated circuit or the second integrated circuit to a package substrate through the external terminal.

Abstract: Systems or methods of the present disclosure may provide a programmable logic device including a network-on-chip (NoC) to facilitate data transfer between one or more main intellectual property components (main IP) and one or more secondary intellectual property components (secondary IP). To reduce or prevent excessive congestion on the NoC, the NoC may include one or more traffic throttlers that may receive feedback from a data buffer, a main bridge, or both and adjust data injection rate based on the feedback. Additionally, the NoC may include a data mapper to enable data transfer to be remapped from a first destination to a second destination if congestion is detected at the first destination.

Abstract: An integrated circuit includes a first input/output lane comprising first external terminals and first driver circuits. The first driver circuits exchange signals with a first external device through the first external terminals as part of a first external interface. The first input/output lane is part of a sub-bank in an input/output bank that implements at least a part of the first external interface. The integrated circuit includes a second input/output lane comprising second external terminals and second driver circuits. The second driver circuits exchange signals with a second external device through the second external terminals as part of a second external interface. The second input/output lane is part of the sub-bank in the input/output bank that implements at least a part of the second external interface.

Abstract: Embodiments of the disclosure relate to systems and methods to reduce power consumption in an integrated circuit (IC) device by controlling various power consuming components of the IC device to a sleep mode when the power consuming components are not in use. The reduction in power consumption by the various power consuming components may reduce power consumption of the IC device in general. In one example, the IC device may include power consuming buffers of data input paths, data output paths, address pin paths, and a clock output path. The IC device may instruct one or more of the power consuming buffers to enter a sleep mode when functions of the one or more power consuming buffers are not in use. In this manner, the IC device may save power while performing various operations (e.g., read/write operations and memory refresh operations).