Abstract: In one embodiment, the invention includes a controller that interrupts a CPU based on a counter that uses a decrement step which may increase as high priority data packets are received by the controller.

Abstract: In one embodiment, the invention includes a controller that interrupts a CPU based on a counter that uses a decrement step which may increase as high priority data packets are received by the controller.

Abstract: A method and apparatus to support communication between components in different clock domains having a rational clock frequency ratio of N/D. In one embodiment, a combination of integer phase generators are employed to produce phase control signals during an overall cycle having N phases, wherein the overall cycle is a combination of primary cycles having D phases and an adjustment cycle having R phases, wherein R is the remainder of N/D. For clock frequency ratios of less than 2:1, a combination of 2:1 and 1:1 phase generators are employed. Clocking signals are generated by phase generator logic to provide timing control between communicating components in the different clock domains. In one embodiment, the phase generator logic is implemented in a programmable phase generator.